From b4a3550b23ad6b7694aa31fe42c25dcc45e8276a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 23 Sep 2019 14:12:49 +0100
Subject: [PATCH]

---
 simple_v_extension/bigint_example.mdwn | 33 ++++++++++++++------------
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/simple_v_extension/bigint_example.mdwn b/simple_v_extension/bigint_example.mdwn
index d2673e32c..8d801db1d 100644
--- a/simple_v_extension/bigint_example.mdwn
+++ b/simple_v_extension/bigint_example.mdwn
@@ -3,21 +3,24 @@
     VBLK.pred.t4 = {t0 }
     VBLK.reg.a0 = {vec}
     VBLK.reg.a1 = {vec}
+    VBLK.reg.t4 = {vec}
     VBLK.VL = 8
-    add t4, a0, a1
-    sub t3, x0, a1 # invert a1
-    BLT a0, t3, cont # stores tests in t0
-    ret
-
+    {
+     add t4, a0, a1
+     sub t3, x0, a1 # invert a1
+     BLT a0, t3, cont # stores tests in t0
+     ret
+    }
     VBLK.pred.t1 = {inv, t0}
-    VBLK.pred.t4 = {t0 }
-    VBLK.reg.a0 = {vec}
-    VBLK.reg.a1 = {vec}
-    cont:
-    slli t0, 1 # shifts up carry by 1
-    addi t4, 1 # predicated on t0
-    BLT t4, t1, cont2 # tests into t0
-    ret
-    cont2:
-    j cont
+    VBLK.pred.t4 = {t0}
+    VBLK.reg.t4 = {vec}
+    {
+     cont:
+     slli t0, t0, 1 # shifts up carry by 1
+     addi t4, t4, 1 # predicated on t0
+     BLT t4, t1, cont2 # tests into t0
+     ret
+     cont2:
+     j cont
+    }
 
-- 
2.30.2