From b4b323c81ee8ea6e756f4c5110f7ac77545325f1 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 14 Aug 2020 23:56:05 -0400 Subject: [PATCH] radeonsi: change PIPE_SHADER to MESA_SHADER (si_shader_context::type) Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- .../drivers/radeonsi/gfx10_shader_ngg.c | 36 +++--- .../radeonsi/si_compute_prim_discard.c | 3 + src/gallium/drivers/radeonsi/si_shader.c | 116 +++++++++--------- .../drivers/radeonsi/si_shader_internal.h | 1 + src/gallium/drivers/radeonsi/si_shader_llvm.c | 33 +++-- .../drivers/radeonsi/si_shader_llvm_gs.c | 6 +- .../drivers/radeonsi/si_shader_llvm_tess.c | 20 +-- 7 files changed, 112 insertions(+), 103 deletions(-) diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c index 00894e23d03..f9415bde279 100644 --- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c +++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c @@ -72,7 +72,7 @@ static LLVMValueRef ngg_get_query_buf(struct si_shader_context *ctx) static LLVMValueRef ngg_get_initial_edgeflag(struct si_shader_context *ctx, unsigned index) { - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { LLVMValueRef tmp; tmp = LLVMBuildLShr(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args.gs_invocation_id), LLVMConstInt(ctx->ac.i32, 8 + index, false), ""); @@ -89,7 +89,7 @@ static LLVMValueRef ngg_get_vertices_per_prim(struct si_shader_context *ctx, uns { const struct si_shader_info *info = &ctx->shader->selector->info; - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) { /* Blits always use axis-aligned rectangles with 3 vertices. */ *num_vertices = 3; @@ -107,7 +107,7 @@ static LLVMValueRef ngg_get_vertices_per_prim(struct si_shader_context *ctx, uns return LLVMBuildAdd(ctx->ac.builder, num, ctx->ac.i32_1, ""); } } else { - assert(ctx->type == PIPE_SHADER_TESS_EVAL); + assert(ctx->stage == MESA_SHADER_TESS_EVAL); if (info->properties[TGSI_PROPERTY_TES_POINT_MODE]) *num_vertices = 1; @@ -282,7 +282,7 @@ static void build_streamout(struct si_shader_context *ctx, struct ngg_streamout LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32); int stream_for_buffer[4] = {-1, -1, -1, -1}; unsigned bufmask_for_stream[4] = {}; - bool isgs = ctx->type == PIPE_SHADER_GEOMETRY; + bool isgs = ctx->stage == MESA_SHADER_GEOMETRY; unsigned scratch_emit_base = isgs ? 4 : 0; LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0; unsigned scratch_offset_base = isgs ? 8 : 4; @@ -770,7 +770,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out bool uses_tes_prim_id = false; LLVMValueRef packed_data = ctx->ac.i32_0; - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { uses_instance_id = sel->info.uses_instanceid || shader->key.part.vs.prolog.instance_divisor_is_one || shader->key.part.vs.prolog.instance_divisor_is_fetched; @@ -786,7 +786,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out } else { uses_tes_prim_id = sel->info.uses_primid || shader->key.mono.u.vs_export_prim_id; - assert(ctx->type == PIPE_SHADER_TESS_EVAL); + assert(ctx->stage == MESA_SHADER_TESS_EVAL); LLVMBuildStore(builder, ac_to_integer(&ctx->ac, ac_get_arg(&ctx->ac, ctx->tes_u)), ac_build_gep0(&ctx->ac, es_vtxptr, LLVMConstInt(ctx->ac.i32, lds_tes_u, 0))); LLVMBuildStore(builder, ac_to_integer(&ctx->ac, ac_get_arg(&ctx->ac, ctx->tes_v)), @@ -1077,7 +1077,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out LLVMBuildStore(builder, tmp, es_data[i]); } - if (ctx->type == PIPE_SHADER_TESS_EVAL) { + if (ctx->stage == MESA_SHADER_TESS_EVAL) { tmp = LLVMBuildLoad(builder, si_build_gep_i8(ctx, old_es_vtxptr, lds_byte2_tes_rel_patch_id), ""); tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, ""); @@ -1100,7 +1100,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out ret = LLVMBuildInsertValue(ctx->ac.builder, ret, new_gs_tg_info, 2, ""); ret = LLVMBuildInsertValue(ctx->ac.builder, ret, new_merged_wave_info, 3, ""); - if (ctx->type == PIPE_SHADER_TESS_EVAL) + if (ctx->stage == MESA_SHADER_TESS_EVAL) ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_offset, 4); ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers, 8 + SI_SGPR_RW_BUFFERS); @@ -1111,7 +1111,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out ret = si_insert_input_ptr(ctx, ret, ctx->samplers_and_images, 8 + SI_SGPR_SAMPLERS_AND_IMAGES); ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { ret = si_insert_input_ptr(ctx, ret, ctx->args.base_vertex, 8 + SI_SGPR_BASE_VERTEX); ret = si_insert_input_ptr(ctx, ret, ctx->args.start_instance, 8 + SI_SGPR_START_INSTANCE); ret = si_insert_input_ptr(ctx, ret, ctx->args.draw_id, 8 + SI_SGPR_DRAWID); @@ -1122,13 +1122,13 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + i * 4); } } else { - assert(ctx->type == PIPE_SHADER_TESS_EVAL); + assert(ctx->stage == MESA_SHADER_TESS_EVAL); ret = si_insert_input_ptr(ctx, ret, ctx->tcs_offchip_layout, 8 + SI_SGPR_TES_OFFCHIP_LAYOUT); ret = si_insert_input_ptr(ctx, ret, ctx->tes_offchip_addr, 8 + SI_SGPR_TES_OFFCHIP_ADDR); } unsigned vgpr; - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { if (shader->selector->num_vbos_in_user_sgprs) { vgpr = 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->num_vbos_in_user_sgprs * 4; } else { @@ -1146,7 +1146,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_invocation_id, vgpr++); vgpr++; /* gs_vtx45_offset */ - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { val = LLVMBuildLoad(builder, es_data[0], ""); ret = LLVMBuildInsertValue(builder, ret, ac_to_float(&ctx->ac, val), vgpr++, ""); /* VGPR5 - VertexID */ @@ -1159,7 +1159,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out vgpr++; } } else { - assert(ctx->type == PIPE_SHADER_TESS_EVAL); + assert(ctx->stage == MESA_SHADER_TESS_EVAL); unsigned num_vgprs = uses_tes_prim_id ? 4 : 3; for (unsigned i = 0; i < num_vgprs; i++) { val = LLVMBuildLoad(builder, es_data[i], ""); @@ -1174,7 +1174,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out /* These two also use LDS. */ if (sel->info.writes_edgeflag || - (ctx->type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id)) + (ctx->stage == MESA_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id)) ac_build_s_barrier(&ctx->ac); ctx->return_value = ret; @@ -1234,7 +1234,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi, unsigned max_outputs, LL bool unterminated_es_if_block = !sel->so.num_outputs && !sel->info.writes_edgeflag && !ctx->screen->use_ngg_streamout && /* no query buffer */ - (ctx->type != PIPE_SHADER_VERTEX || !ctx->shader->key.mono.u.vs_export_prim_id); + (ctx->stage != MESA_SHADER_VERTEX || !ctx->shader->key.mono.u.vs_export_prim_id); if (!unterminated_es_if_block) ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label); @@ -1301,7 +1301,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi, unsigned max_outputs, LL /* Copy Primitive IDs from GS threads to the LDS address corresponding * to the ES thread of the provoking vertex. */ - if (ctx->type == PIPE_SHADER_VERTEX && ctx->shader->key.mono.u.vs_export_prim_id) { + if (ctx->stage == MESA_SHADER_VERTEX && ctx->shader->key.mono.u.vs_export_prim_id) { assert(!unterminated_es_if_block); /* Streamout and edge flags use LDS. Make it idle, so that we can reuse it. */ @@ -1398,7 +1398,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi, unsigned max_outputs, LL outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID; outputs[i].semantic_index = 0; - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { /* Wait for GS stores to finish. */ ac_build_s_barrier(&ctx->ac); @@ -1406,7 +1406,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi, unsigned max_outputs, LL tmp = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0); outputs[i].values[0] = LLVMBuildLoad(builder, tmp, ""); } else { - assert(ctx->type == PIPE_SHADER_TESS_EVAL); + assert(ctx->stage == MESA_SHADER_TESS_EVAL); outputs[i].values[0] = si_get_primitive_id(ctx, 0); } diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c index 757fc8b031b..c8c8f1159db 100644 --- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c +++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c @@ -347,9 +347,12 @@ void si_build_prim_discard_compute_shader(struct si_shader_context *ctx) /* Create the compute shader function. */ unsigned old_type = ctx->type; + gl_shader_stage old_stage = ctx->stage; ctx->type = PIPE_SHADER_COMPUTE; + ctx->stage = MESA_SHADER_COMPUTE; si_llvm_create_func(ctx, "prim_discard_cs", NULL, 0, THREADGROUP_SIZE); ctx->type = old_type; + ctx->stage = old_stage; if (VERTEX_COUNTER_GDS_MODE == 2) { ac_llvm_add_target_dep_function_attr(ctx->main_fn, "amdgpu-gds-size", 256); diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 0df816b0075..da1f8435da0 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -159,7 +159,7 @@ static void declare_streamout_params(struct si_shader_context *ctx, struct pipe_stream_output_info *so) { if (ctx->screen->use_ngg_streamout) { - if (ctx->type == PIPE_SHADER_TESS_EVAL) + if (ctx->stage == MESA_SHADER_TESS_EVAL) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); return; } @@ -168,7 +168,7 @@ static void declare_streamout_params(struct si_shader_context *ctx, if (so->num_outputs) { ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->streamout_config); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->streamout_write_index); - } else if (ctx->type == PIPE_SHADER_TESS_EVAL) { + } else if (ctx->stage == MESA_SHADER_TESS_EVAL) { ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); } @@ -378,21 +378,21 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) unsigned i, num_return_sgprs; unsigned num_returns = 0; unsigned num_prolog_vgprs = 0; - unsigned type = ctx->type; + unsigned stage = ctx->stage; unsigned vs_blit_property = shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]; memset(&ctx->args, 0, sizeof(ctx->args)); /* Set MERGED shaders. */ if (ctx->screen->info.chip_class >= GFX9) { - if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL) - type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */ - else if (shader->key.as_es || shader->key.as_ngg || type == PIPE_SHADER_GEOMETRY) - type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY; + if (shader->key.as_ls || stage == MESA_SHADER_TESS_CTRL) + stage = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */ + else if (shader->key.as_es || shader->key.as_ngg || stage == MESA_SHADER_GEOMETRY) + stage = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY; } - switch (type) { - case PIPE_SHADER_VERTEX: + switch (stage) { + case MESA_SHADER_VERTEX: declare_global_desc_pointers(ctx); if (vs_blit_property) { @@ -427,7 +427,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) } break; - case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */ + case MESA_SHADER_TESS_CTRL: /* GFX6-GFX8 */ declare_global_desc_pointers(ctx); declare_per_stage_desc_pointers(ctx, true); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout); @@ -453,7 +453,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) case SI_SHADER_MERGED_VERTEX_TESSCTRL: /* Merged stages have 8 system SGPRs at the beginning. */ /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */ - declare_per_stage_desc_pointers(ctx, ctx->type == PIPE_SHADER_TESS_CTRL); + declare_per_stage_desc_pointers(ctx, ctx->stage == MESA_SHADER_TESS_CTRL); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_offset); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->merged_wave_info); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_factor_offset); @@ -462,7 +462,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused */ declare_global_desc_pointers(ctx); - declare_per_stage_desc_pointers(ctx, ctx->type == PIPE_SHADER_VERTEX); + declare_per_stage_desc_pointers(ctx, ctx->stage == MESA_SHADER_VERTEX); declare_vs_specific_input_sgprs(ctx); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout); @@ -474,7 +474,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tcs_patch_id); ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.tcs_rel_ids); - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { declare_vs_input_vgprs(ctx, &num_prolog_vgprs, ngg_cull_shader); /* LS return values are inputs to the TCS main shader part. */ @@ -499,7 +499,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY: /* Merged stages have 8 system SGPRs at the beginning. */ /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */ - declare_per_stage_desc_pointers(ctx, ctx->type == PIPE_SHADER_GEOMETRY); + declare_per_stage_desc_pointers(ctx, ctx->stage == MESA_SHADER_GEOMETRY); if (ctx->shader->key.as_ngg) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs_tg_info); @@ -515,12 +515,12 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) NULL); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */ declare_global_desc_pointers(ctx); - if (ctx->type != PIPE_SHADER_VERTEX || !vs_blit_property) { + if (ctx->stage != MESA_SHADER_VERTEX || !vs_blit_property) { declare_per_stage_desc_pointers( - ctx, (ctx->type == PIPE_SHADER_VERTEX || ctx->type == PIPE_SHADER_TESS_EVAL)); + ctx, (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL)); } - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { if (vs_blit_property) declare_vs_blit_inputs(ctx, vs_blit_property); else @@ -532,7 +532,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) /* Declare as many input SGPRs as the VS has. */ } - if (ctx->type == PIPE_SHADER_VERTEX) + if (ctx->stage == MESA_SHADER_VERTEX) declare_vb_descriptor_input_sgprs(ctx); /* VGPRs (first GS, then VS/TES) */ @@ -542,17 +542,17 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_invocation_id); ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->gs_vtx45_offset); - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { declare_vs_input_vgprs(ctx, &num_prolog_vgprs, ngg_cull_shader); - } else if (ctx->type == PIPE_SHADER_TESS_EVAL) { + } else if (ctx->stage == MESA_SHADER_TESS_EVAL) { declare_tes_input_vgprs(ctx, ngg_cull_shader); } if ((ctx->shader->key.as_es || ngg_cull_shader) && - (ctx->type == PIPE_SHADER_VERTEX || ctx->type == PIPE_SHADER_TESS_EVAL)) { + (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL)) { unsigned num_user_sgprs, num_vgprs; - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { /* For the NGG cull shader, add 1 SGPR to hold * the vertex buffer pointer. */ @@ -582,7 +582,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) } break; - case PIPE_SHADER_TESS_EVAL: + case MESA_SHADER_TESS_EVAL: declare_global_desc_pointers(ctx); declare_per_stage_desc_pointers(ctx, true); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits); @@ -602,7 +602,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) declare_tes_input_vgprs(ctx, ngg_cull_shader); break; - case PIPE_SHADER_GEOMETRY: + case MESA_SHADER_GEOMETRY: declare_global_desc_pointers(ctx); declare_per_stage_desc_pointers(ctx, true); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs2vs_offset); @@ -619,7 +619,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_invocation_id); break; - case PIPE_SHADER_FRAGMENT: + case MESA_SHADER_FRAGMENT: declare_global_desc_pointers(ctx); declare_per_stage_desc_pointers(ctx, true); si_add_arg_checked(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL, SI_PARAM_ALPHA_REF); @@ -683,7 +683,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) returns[i] = ctx->ac.f32; break; - case PIPE_SHADER_COMPUTE: + case MESA_SHADER_COMPUTE: declare_global_desc_pointers(ctx); declare_per_stage_desc_pointers(ctx, true); if (shader->selector->info.uses_grid_size) @@ -737,7 +737,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) si_get_max_workgroup_size(shader)); /* Reserve register locations for VGPR inputs the PS prolog may need. */ - if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) { + if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->shader->is_monolithic) { ac_llvm_add_target_dep_function_attr( ctx->main_fn, "InitialPSInputAddr", S_0286D0_PERSP_SAMPLE_ENA(1) | S_0286D0_PERSP_CENTER_ENA(1) | @@ -752,7 +752,7 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) assert(shader->info.num_input_vgprs >= num_prolog_vgprs); shader->info.num_input_vgprs -= num_prolog_vgprs; - if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) { + if (shader->key.as_ls || ctx->stage == MESA_SHADER_TESS_CTRL) { if (USE_LDS_SYMBOLS && LLVM_VERSION_MAJOR >= 9) { /* The LSHS size is not known until draw time, so we append it * at the end of whatever LDS use there may be in the rest of @@ -770,10 +770,10 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader) /* Unlike radv, we override these arguments in the prolog, so to the * API shader they appear as normal arguments. */ - if (ctx->type == PIPE_SHADER_VERTEX) { + if (ctx->stage == MESA_SHADER_VERTEX) { ctx->abi.vertex_id = ac_get_arg(&ctx->ac, ctx->args.vertex_id); ctx->abi.instance_id = ac_get_arg(&ctx->ac, ctx->args.instance_id); - } else if (ctx->type == PIPE_SHADER_FRAGMENT) { + } else if (ctx->stage == MESA_SHADER_FRAGMENT) { ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args.persp_centroid); ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args.linear_centroid); } @@ -1296,7 +1296,7 @@ static void si_optimize_vs_outputs(struct si_shader_context *ctx) struct si_shader_info *info = &shader->selector->info; unsigned skip_vs_optim_mask = 0; - if ((ctx->type != PIPE_SHADER_VERTEX && ctx->type != PIPE_SHADER_TESS_EVAL) || + if ((ctx->stage != MESA_SHADER_VERTEX && ctx->stage != MESA_SHADER_TESS_EVAL) || shader->key.as_ls || shader->key.as_es) return; @@ -1333,6 +1333,7 @@ static bool si_build_main_function(struct si_shader_context *ctx, struct si_shad ctx->shader = shader; ctx->type = sel->type; + ctx->stage = sel->info.stage; ctx->num_const_buffers = util_last_bit(info->const_buffers_declared); ctx->num_shader_buffers = util_last_bit(info->shader_buffers_declared); @@ -1342,23 +1343,23 @@ static bool si_build_main_function(struct si_shader_context *ctx, struct si_shad si_llvm_init_resource_callbacks(ctx); - switch (ctx->type) { - case PIPE_SHADER_VERTEX: + switch (ctx->stage) { + case MESA_SHADER_VERTEX: si_llvm_init_vs_callbacks(ctx, ngg_cull_shader); break; - case PIPE_SHADER_TESS_CTRL: + case MESA_SHADER_TESS_CTRL: si_llvm_init_tcs_callbacks(ctx); break; - case PIPE_SHADER_TESS_EVAL: + case MESA_SHADER_TESS_EVAL: si_llvm_init_tes_callbacks(ctx, ngg_cull_shader); break; - case PIPE_SHADER_GEOMETRY: + case MESA_SHADER_GEOMETRY: si_llvm_init_gs_callbacks(ctx); break; - case PIPE_SHADER_FRAGMENT: + case MESA_SHADER_FRAGMENT: si_llvm_init_ps_callbacks(ctx); break; - case PIPE_SHADER_COMPUTE: + case MESA_SHADER_COMPUTE: ctx->abi.load_local_group_size = si_llvm_get_block_size; break; default: @@ -1368,21 +1369,21 @@ static bool si_build_main_function(struct si_shader_context *ctx, struct si_shad si_create_function(ctx, ngg_cull_shader); - if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) + if (ctx->shader->key.as_es || ctx->stage == MESA_SHADER_GEOMETRY) si_preload_esgs_ring(ctx); - if (ctx->type == PIPE_SHADER_GEOMETRY) + if (ctx->stage == MESA_SHADER_GEOMETRY) si_preload_gs_rings(ctx); - else if (ctx->type == PIPE_SHADER_TESS_EVAL) + else if (ctx->stage == MESA_SHADER_TESS_EVAL) si_llvm_preload_tes_rings(ctx); - if (ctx->type == PIPE_SHADER_TESS_CTRL && sel->info.tessfactors_are_def_in_all_invocs) { + if (ctx->stage == MESA_SHADER_TESS_CTRL && sel->info.tessfactors_are_def_in_all_invocs) { for (unsigned i = 0; i < 6; i++) { ctx->invoc0_tess_factors[i] = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, ""); } } - if (ctx->type == PIPE_SHADER_GEOMETRY) { + if (ctx->stage == MESA_SHADER_GEOMETRY) { for (unsigned i = 0; i < 4; i++) { ctx->gs_next_vertex[i] = ac_build_alloca(&ctx->ac, ctx->ac.i32, ""); } @@ -1406,7 +1407,7 @@ static bool si_build_main_function(struct si_shader_context *ctx, struct si_shad } } - if (ctx->type != PIPE_SHADER_GEOMETRY && (shader->key.as_ngg && !shader->key.as_es)) { + if (ctx->stage != MESA_SHADER_GEOMETRY && (shader->key.as_ngg && !shader->key.as_es)) { /* Unconditionally declare scratch space base for streamout and * vertex compaction. Whether space is actually allocated is * determined during linking / PM4 creation. @@ -1447,20 +1448,20 @@ static bool si_build_main_function(struct si_shader_context *ctx, struct si_shad */ if (ctx->screen->info.chip_class >= GFX9) { if (!shader->is_monolithic && (shader->key.as_es || shader->key.as_ls) && - (ctx->type == PIPE_SHADER_TESS_EVAL || - (ctx->type == PIPE_SHADER_VERTEX && + (ctx->stage == MESA_SHADER_TESS_EVAL || + (ctx->stage == MESA_SHADER_VERTEX && !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog, &shader->key, ngg_cull_shader)))) { si_init_exec_from_input(ctx, ctx->merged_wave_info, 0); - } else if (ctx->type == PIPE_SHADER_TESS_CTRL || ctx->type == PIPE_SHADER_GEOMETRY || + } else if (ctx->stage == MESA_SHADER_TESS_CTRL || ctx->stage == MESA_SHADER_GEOMETRY || (shader->key.as_ngg && !shader->key.as_es)) { LLVMValueRef thread_enabled; bool nested_barrier; - if (!shader->is_monolithic || (ctx->type == PIPE_SHADER_TESS_EVAL && shader->key.as_ngg && + if (!shader->is_monolithic || (ctx->stage == MESA_SHADER_TESS_EVAL && shader->key.as_ngg && !shader->key.as_es && !shader->key.opt.ngg_culling)) ac_init_exec_full_mask(&ctx->ac); - if ((ctx->type == PIPE_SHADER_VERTEX || ctx->type == PIPE_SHADER_TESS_EVAL) && + if ((ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL) && shader->key.as_ngg && !shader->key.as_es && !shader->key.opt.ngg_culling) { gfx10_ngg_build_sendmsg_gs_alloc_req(ctx); @@ -1471,8 +1472,8 @@ static bool si_build_main_function(struct si_shader_context *ctx, struct si_shad gfx10_ngg_build_export_prim(ctx, NULL, NULL); } - if (ctx->type == PIPE_SHADER_TESS_CTRL || ctx->type == PIPE_SHADER_GEOMETRY) { - if (ctx->type == PIPE_SHADER_GEOMETRY && shader->key.as_ngg) { + if (ctx->stage == MESA_SHADER_TESS_CTRL || ctx->stage == MESA_SHADER_GEOMETRY) { + if (ctx->stage == MESA_SHADER_GEOMETRY && shader->key.as_ngg) { gfx10_ngg_gs_emit_prologue(ctx); nested_barrier = false; } else { @@ -1637,7 +1638,7 @@ static bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_com return false; } - if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) { + if (shader->is_monolithic && ctx.stage == MESA_SHADER_VERTEX) { LLVMValueRef parts[4]; unsigned num_parts = 0; bool has_prolog = false; @@ -1671,14 +1672,14 @@ static bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_com if (ctx.shader->key.opt.vs_as_prim_discard_cs) si_build_prim_discard_compute_shader(&ctx); - } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL && ngg_cull_main_fn) { + } else if (shader->is_monolithic && ctx.stage == MESA_SHADER_TESS_EVAL && ngg_cull_main_fn) { LLVMValueRef parts[2]; parts[0] = ngg_cull_main_fn; parts[1] = ctx.main_fn; si_build_wrapper_function(&ctx, parts, 2, 0, 0); - } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) { + } else if (shader->is_monolithic && ctx.stage == MESA_SHADER_TESS_CTRL) { if (sscreen->info.chip_class >= GFX9) { struct si_shader_selector *ls = shader->key.part.tcs.ls; LLVMValueRef parts[4]; @@ -1724,6 +1725,7 @@ static bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_com /* Reset the shader context. */ ctx.shader = shader; ctx.type = PIPE_SHADER_TESS_CTRL; + ctx.stage = MESA_SHADER_TESS_CTRL; si_build_wrapper_function(&ctx, parts + !vs_needs_prolog, 4 - !vs_needs_prolog, vs_needs_prolog, vs_needs_prolog ? 2 : 1); @@ -1740,7 +1742,7 @@ static bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_com si_build_wrapper_function(&ctx, parts, 2, 0, 0); } - } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) { + } else if (shader->is_monolithic && ctx.stage == MESA_SHADER_GEOMETRY) { if (ctx.screen->info.chip_class >= GFX9) { struct si_shader_selector *es = shader->key.part.gs.es; LLVMValueRef es_prolog = NULL; @@ -1788,6 +1790,7 @@ static bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_com /* Reset the shader context. */ ctx.shader = shader; ctx.type = PIPE_SHADER_GEOMETRY; + ctx.stage = MESA_SHADER_GEOMETRY; /* Prepare the array of shader parts. */ LLVMValueRef parts[4]; @@ -1814,7 +1817,7 @@ static bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_com si_build_wrapper_function(&ctx, parts, 2, 1, 0); } - } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) { + } else if (shader->is_monolithic && ctx.stage == MESA_SHADER_FRAGMENT) { si_llvm_build_monolithic_ps(&ctx, shader); } @@ -1994,6 +1997,7 @@ si_get_shader_part(struct si_screen *sscreen, struct si_shader_part **list, shader.key.opt.vs_as_prim_discard_cs)); ctx.shader = &shader; ctx.type = type; + ctx.stage = tgsi_processor_to_shader_stage(type); build(&ctx, key); diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index b31a9f4fde1..6413085d5b2 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -50,6 +50,7 @@ struct si_shader_context { struct si_screen *screen; unsigned type; /* PIPE_SHADER_* specifies the type of shader. */ + gl_shader_stage stage; /* For clamping the non-constant index in resource indexing: */ unsigned num_const_buffers; diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index 32d436aeacb..51072c1efc9 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -142,38 +142,37 @@ void si_llvm_create_func(struct si_shader_context *ctx, const char *name, LLVMTy { LLVMTypeRef ret_type; enum ac_llvm_calling_convention call_conv; - enum pipe_shader_type real_shader_type; if (num_return_elems) ret_type = LLVMStructTypeInContext(ctx->ac.context, return_types, num_return_elems, true); else ret_type = ctx->ac.voidt; - real_shader_type = ctx->type; + gl_shader_stage real_stage = ctx->stage; /* LS is merged into HS (TCS), and ES is merged into GS. */ if (ctx->screen->info.chip_class >= GFX9) { if (ctx->shader->key.as_ls) - real_shader_type = PIPE_SHADER_TESS_CTRL; + real_stage = MESA_SHADER_TESS_CTRL; else if (ctx->shader->key.as_es || ctx->shader->key.as_ngg) - real_shader_type = PIPE_SHADER_GEOMETRY; + real_stage = MESA_SHADER_GEOMETRY; } - switch (real_shader_type) { - case PIPE_SHADER_VERTEX: - case PIPE_SHADER_TESS_EVAL: + switch (real_stage) { + case MESA_SHADER_VERTEX: + case MESA_SHADER_TESS_EVAL: call_conv = AC_LLVM_AMDGPU_VS; break; - case PIPE_SHADER_TESS_CTRL: + case MESA_SHADER_TESS_CTRL: call_conv = AC_LLVM_AMDGPU_HS; break; - case PIPE_SHADER_GEOMETRY: + case MESA_SHADER_GEOMETRY: call_conv = AC_LLVM_AMDGPU_GS; break; - case PIPE_SHADER_FRAGMENT: + case MESA_SHADER_FRAGMENT: call_conv = AC_LLVM_AMDGPU_PS; break; - case PIPE_SHADER_COMPUTE: + case MESA_SHADER_COMPUTE: call_conv = AC_LLVM_AMDGPU_CS; break; default: @@ -282,7 +281,7 @@ void si_llvm_emit_barrier(struct si_shader_context *ctx) * The real barrier instruction isn’t needed, because an entire patch * always fits into a single wave. */ - if (ctx->screen->info.chip_class == GFX6 && ctx->type == PIPE_SHADER_TESS_CTRL) { + if (ctx->screen->info.chip_class == GFX6 && ctx->stage == MESA_SHADER_TESS_CTRL) { ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE); return; } @@ -351,14 +350,14 @@ LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx, unsigned swizzle if (swizzle > 0) return ctx->ac.i32_0; - switch (ctx->type) { - case PIPE_SHADER_VERTEX: + switch (ctx->stage) { + case MESA_SHADER_VERTEX: return ac_get_arg(&ctx->ac, ctx->vs_prim_id); - case PIPE_SHADER_TESS_CTRL: + case MESA_SHADER_TESS_CTRL: return ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id); - case PIPE_SHADER_TESS_EVAL: + case MESA_SHADER_TESS_EVAL: return ac_get_arg(&ctx->ac, ctx->args.tes_patch_id); - case PIPE_SHADER_GEOMETRY: + case MESA_SHADER_GEOMETRY: return ac_get_arg(&ctx->ac, ctx->args.gs_prim_id); default: assert(0); diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c index 0cda555328e..c28fe59e92f 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c @@ -162,7 +162,7 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx) } unsigned vgpr; - if (ctx->type == PIPE_SHADER_VERTEX) + if (ctx->stage == MESA_SHADER_VERTEX) vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR; else vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR; @@ -360,7 +360,7 @@ static void si_llvm_emit_primitive(struct ac_shader_abi *abi, unsigned stream) void si_preload_esgs_ring(struct si_shader_context *ctx) { if (ctx->screen->info.chip_class <= GFX8) { - unsigned ring = ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS : SI_ES_RING_ESGS; + unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? SI_GS_RING_ESGS : SI_ES_RING_ESGS; LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, 0); LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers); @@ -478,6 +478,7 @@ struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen, false, false, false, false)); ctx.shader = shader; ctx.type = PIPE_SHADER_VERTEX; + ctx.stage = MESA_SHADER_VERTEX; builder = ctx.ac.builder; @@ -564,6 +565,7 @@ struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen, LLVMBuildRetVoid(ctx.ac.builder); ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */ + ctx.stage = MESA_SHADER_GEOMETRY; /* override for shader dumping */ si_llvm_optimize_module(&ctx); bool ok = false; diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c index f27623ad514..e0c5142edf0 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c @@ -28,11 +28,11 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx) { - switch (ctx->type) { - case PIPE_SHADER_TESS_CTRL: + switch (ctx->stage) { + case MESA_SHADER_TESS_CTRL: return si_unpack_param(ctx, ctx->args.tcs_rel_ids, 0, 8); - case PIPE_SHADER_TESS_EVAL: + case MESA_SHADER_TESS_EVAL: return ac_get_arg(&ctx->ac, ctx->tes_rel_patch_id); default: @@ -69,7 +69,7 @@ static LLVMValueRef get_tcs_in_patch_stride(struct si_shader_context *ctx) static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx) { - assert(ctx->type == PIPE_SHADER_TESS_CTRL); + assert(ctx->stage == MESA_SHADER_TESS_CTRL); if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4; @@ -142,7 +142,7 @@ static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx) : 0; /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */ - if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices) + if (ctx->stage == MESA_SHADER_TESS_CTRL && tcs_out_vertices) return LLVMConstInt(ctx->ac.i32, tcs_out_vertices, 0); return si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 6); @@ -152,12 +152,12 @@ static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx) { unsigned stride; - switch (ctx->type) { - case PIPE_SHADER_VERTEX: + switch (ctx->stage) { + case MESA_SHADER_VERTEX: stride = ctx->shader->selector->lshs_vertex_stride / 4; return LLVMConstInt(ctx->ac.i32, stride, 0); - case PIPE_SHADER_TESS_CTRL: + case MESA_SHADER_TESS_CTRL: if (ctx->screen->info.chip_class >= GFX9 && ctx->shader->is_monolithic) { stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4; return LLVMConstInt(ctx->ac.i32, stride, 0); @@ -688,9 +688,9 @@ static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi, unsigned varyi static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi) { struct si_shader_context *ctx = si_shader_context_from_abi(abi); - if (ctx->type == PIPE_SHADER_TESS_CTRL) + if (ctx->stage == MESA_SHADER_TESS_CTRL) return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 13, 6); - else if (ctx->type == PIPE_SHADER_TESS_EVAL) + else if (ctx->stage == MESA_SHADER_TESS_EVAL) return get_num_tcs_out_vertices(ctx); else unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN"); -- 2.30.2