From b4bc2ceb3940414e80b3558371fcaa9a741084bd Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 20 May 2022 22:57:18 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 6d3708f68..445083ef7 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -255,7 +255,10 @@ to deriving the Vectorised versions of these instructions. Normally the progression of the SV for-loop would move on to the next register. Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** -of the scalar integer source or destination. +of the scalar integer source or destination. The reason is that when +using CR Fields as predicate masks and there is a need to transfer +into a GPR, again for use as a predicate mask, the CR Field bits +need to be efficiently packed into that one GPR (r3, r10 or r31). Further useful violation of the normal SV Elwidth override rules allows for packing (or unpacking) of multiple CR test results into (or out of) -- 2.30.2