From b4bfb7a74954526a118b0f9609a1f100a1ad3b78 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Jun 2019 16:05:27 +0100 Subject: [PATCH] add SV VLIW idea --- simple_v_extension/specification.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index a6ea3e874..2004f5aaa 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2230,10 +2230,10 @@ Optional VL/MAXVL/SubVL Block: Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: -| base+4 | base+2 | base | number of bits | +^ base+4 ^ base+2 ^ base ^ number of bits ^ | ------ | ---------------- | ---------------- | -------------------------- | | ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | -|| {ops}{Pred}{Reg}{VL} | SV Prefix | | +| {ops}{Pred}{Reg}{VL} || SV Prefix | | Notes: -- 2.30.2