From b4dcb90c2bb022345090c3f2c47ab24328a529d3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Nov 2021 16:34:57 +0000 Subject: [PATCH] code comments --- src/soc/simple/core.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index f9dc2dc1..5ffee737 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -70,6 +70,23 @@ def sort_fuspecs(fuspecs): class CoreInput: + """CoreInput: this is the input specification for Signals coming into core. + + * state. this contains PC, MSR, and SVSTATE. this is crucial information. + (TODO: bigendian_i should really be read from the relevant MSR bit) + + * the previously-decoded instruction goes into the Decode2Execute1Type + data structure. no need for Core to re-decode that. however note + that *satellite* decoders *are* part of Core. + + * the raw instruction. this is used by satellite decoders internal to + Core, to provide Function-Unit-specific information. really, they + should be part of the actual ALU itself (in order to reduce wires), + but hey. + + * other stuff is related to SVP64. the 24-bit SV REMAP field containing + Vector context, etc. + """ def __init__(self, pspec, svp64_en, regreduce_en): self.pspec = pspec self.svp64_en = svp64_en -- 2.30.2