From b4dcd8e61c889521c9ded626528122558052966c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 14:58:03 +0100
Subject: [PATCH] add vector-vector sv add

---
 isa/macros/simplev/sv_test_macros.h |  4 ++
 isa/rv64ui/Makefrag.sv              |  1 +
 isa/rv64ui/sv_addi_vector_vector.S  | 62 +++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+)
 create mode 100644 isa/rv64ui/sv_addi_vector_vector.S

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 22eb2b1..97bb950 100644
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -12,6 +12,10 @@
         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
         csrrw  x0, 0x4c8, x1
 
+#define SET_SV_2CSRS( c1, c2 ) \
+        li     x1, c1 | ((c2)<<16); \
+        csrrw  x0, 0x4c0, x1
+
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index 9e79ca5..da91e06 100644
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -6,6 +6,7 @@ rv64ui_sv_tests = \
 	sv_addi \
 	sv_addi_redirect \
 	sv_addi_scalar_src \
+	sv_addi_vector_vector \
 	sv_addi_predicated \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S
new file mode 100644
index 0000000..ea1f3c6
--- /dev/null
+++ b/isa/rv64ui/sv_addi_vector_vector.S
@@ -0,0 +1,62 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+
+# SV test: vector-vector add different rd and rs1
+#
+# sets up x6 and x7 with data, sets VL to 2, and carries out
+# an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_LD_DATA( x2, testdata   , 0)
+        SV_LD_DATA( x6, testdata+8 , 0)
+        SV_LD_DATA( x7, testdata+16, 0)
+        SV_LD_DATA( x5, testdata+24, 0)
+
+        li          x3, 0 # deliberately set x3 to 0 (target of add)
+        li          x4, 0 # deliberately set x4 to 0
+
+        SET_SV_MVL(2)
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
+                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
+        SET_SV_VL(2)
+
+        addi    x3, x6, 1
+
+        CLR_SV_CSRS()
+        SET_SV_VL(0)
+        SET_SV_MVL(0)
+
+        TEST_SV_IMM(x2, 1001) # should not be modified
+        TEST_SV_IMM(x3, 42)
+        TEST_SV_IMM(x4, 43)
+        TEST_SV_IMM(x5, 1002) # should not be modified
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 41
+        .dword 42
+        .dword 1002
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+
-- 
2.30.2