From b4e5ec711a77011d7f8576a2fb7e0ea1a037d278 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 May 2023 21:06:56 +0100 Subject: [PATCH] CROpFF3RM and CROpFF5RM were swapped round. FF3 has the CR-bit (and only zz - bit 6) FF5 has only the inv-bit --- src/openpower/decoder/power_insn.py | 17 ++++++++--------- src/openpower/sv/trans/test_pysvp64dis.py | 12 ++++++------ 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 3a4bee10..1e3a2e73 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -2330,10 +2330,10 @@ class CROpMRRM(MRBaseRM, ZZCombinedBaseRM, CROpBaseRM): sz: BaseRM[23] -class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM): - """crop: ffirst 3-bit mode""" +class CROpFF5RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM): + """crop: ffirst 5-bit mode""" VLi: BaseRM[19] - RC1 = 0 + RC1 = 1 inv: BaseRM[21] dz: BaseRM[22] sz: BaseRM[23] @@ -2342,12 +2342,11 @@ class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CRO yield from super().specifiers(record=record, mode="ff") -# FIXME: almost everything in this class contradicts the specs. -# However, this is the direct translation of the pysvp64asm code. -# Please revisit this code; there is an inactive sketch below. -class CROpFF5RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, CROpBaseRM): - """cr_op: ffirst 5-bit mode""" - RC1 = 1 # temporary hack +# FIXME: almost everything in this class contradicts the specs (it doesn't) +# The modes however are swapped: 5-bit is 3-bit, 3-bit is 5-bit +class CROpFF3RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, CROpBaseRM): + """cr_op: ffirst 3-bit mode""" + RC1 = 0 # temporary hack VLi: BaseRM[19] inv: BaseRM[21] CR: BaseRM[22, 23] diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index e548a304..273abaff 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -315,12 +315,12 @@ class SVSTATETestCase(unittest.TestCase): def test_20_cmp(self): expected = [ "sv.cmp *4,1,*0,1", - "sv.cmp/ff=RC1 *4,1,*0,1", - "sv.cmp/ff=RC1/vli *4,1,*0,1", - "sv.cmp/ff=~RC1 *4,1,*0,1", - "sv.cmp/ff=RC1/m=r3/sz *4,1,*0,1", - "sv.cmp/dz/ff=RC1/m=r3 *4,1,*0,1", - "sv.cmp/dz/ff=RC1/m=r3/sz *4,1,*0,1", + "sv.cmp/ff=eq *4,1,*0,1", + "sv.cmp/ff=eq/vli *4,1,*0,1", + "sv.cmp/ff=ne *4,1,*0,1", + "sv.cmp/ff=eq/m=r3/sz *4,1,*0,1", + "sv.cmp/dz/ff=lt/m=r3 *4,1,*0,1", + "sv.cmp/dz/ff=gt/m=r3/sz *4,1,*0,1", ] self._do_tst(expected) -- 2.30.2