From b4f3973f304becddc7da2471536dfef014e8f95d Mon Sep 17 00:00:00 2001 From: james Date: Thu, 23 Nov 2023 12:10:16 +0000 Subject: [PATCH] --- nlnet_2023_svp64_riscv.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn index 7055026b7..94dbc23e9 100644 --- a/nlnet_2023_svp64_riscv.mdwn +++ b/nlnet_2023_svp64_riscv.mdwn @@ -53,19 +53,29 @@ EUR 100,000. Key phases of this project are: + * Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions whereas POWER ISA SFFS is 214) which are present in Power ISA 3.0 + * Implementation of the missing RISC-V instructions and instruction forms that makes is comparable with POWER ISA in the Scalar ISA space. + * Assessment of application of Simple-V Vector Prefixing to SVP64, building on the work already done under NLnet Grant 2019-10-012 + * Implementation of Simple-V in the Libre-SOC Simulator, ISACaller. + * Assembler and disassembler of RISC-V instructions and also SVP64 in the Libre-SOC infrastructure. + * Upgrading (with the newly created instructions and forms) sv-spike assembler development which was prototyped previously for Simple-V Specification: + * Adding a comprehensive unit test base for the new instructions which can then be tested against sv-spike as well as ISACaller. Conversion of previously created instructions to the new format used in Libre-SOC, and adding the newly defined and created instructions. + * Documentation, demonstrations and Conference Papers. This will include porting results of other completed projects (cryptoprimitives, video) from POWER ISA to the RISC-V/Simple-V/SVP64 environment + * Research and assessment of ARM7 and i486 (both on opencores.org)as to their feasibility for applying Simple-V Prefixing in future development projects + # Does the project have other funding sources, both past and present? NGI Search, NGI POINTER, and NLnet Grants have been the sole source of funding -- 2.30.2