From b53315bf305f6ff1bbb3fe74a6a28effc2a84eed Mon Sep 17 00:00:00 2001 From: Nikos Nikoleris Date: Mon, 24 Feb 2020 18:58:07 +0200 Subject: [PATCH] configs: Fix argument handling sweep.py Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc Signed-off-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25710 Reviewed-by: Daniel Carvalho Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- configs/common/ObjectList.py | 15 +++++++++++++++ configs/dram/sweep.py | 11 +++++------ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py index 875fc9462..8bffa5fe0 100644 --- a/configs/common/ObjectList.py +++ b/configs/common/ObjectList.py @@ -150,11 +150,26 @@ class CPUList(ObjectList): self._is_obj_class): self._sub_classes[name] = cls +class EnumList(ObjectList): + """ Creates a list of possible values for a given enum class. """ + + def _add_objects(self): + """ Add all enum values to the ObjectList """ + self._sub_classes = {} + for (key, value) in self.base_cls.__members__.items(): + # All Enums have a value Num_NAME at the end which we + # do not want to include + if not key.startswith("Num_"): + self._sub_classes[key] = value + + bp_list = ObjectList(getattr(m5.objects, 'BranchPredictor', None)) cpu_list = CPUList(getattr(m5.objects, 'BaseCPU', None)) hwp_list = ObjectList(getattr(m5.objects, 'BasePrefetcher', None)) indirect_bp_list = ObjectList(getattr(m5.objects, 'IndirectPredictor', None)) mem_list = ObjectList(getattr(m5.objects, 'AbstractMemory', None)) +dram_addr_map_list = EnumList(getattr(m5.internal.params, 'enum_AddrMap', + None)) # Platform aliases. The platforms listed here might not be compiled, # we make sure they exist before we add them to the platform list. diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index f1f97dc4f..c2650a72f 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -77,9 +77,9 @@ parser.add_option("--mode", type="choice", default="DRAM", help = "DRAM: Random traffic; \ DRAM_ROTATE: Traffic rotating across banks and ranks") -parser.add_argument("--addr-map", - choices=m5.objects.AddrMap.vals, - default="RoRaBaCoCh", help = "DRAM address map policy") +parser.add_option("--addr-map", type="choice", + choices=ObjectList.dram_addr_map_list.get_names(), + default="RoRaBaCoCh", help = "DRAM address map policy") (options, args) = parser.parse_args() @@ -122,7 +122,7 @@ if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): system.mem_ctrls[0].null = True # Set the address mapping based on input argument -system.mem_ctrls[0].addr_mapping = args.addr_map +system.mem_ctrls[0].addr_mapping = options.addr_map # stay in each state for 0.25 ms, long enough to warm things up, and # short enough to avoid hitting a refresh @@ -177,9 +177,8 @@ root.system.mem_mode = 'timing' m5.instantiate() -addr_map = m5.objects.AddrMap.map[args.addr_map] - def trace(): + addr_map = ObjectList.dram_addr_map_list.get(options.addr_map) generator = dram_generators[options.mode](system.tgen) for bank in range(1, nbr_banks + 1): for stride_size in range(burst_size, max_stride + 1, burst_size): -- 2.30.2