From b5352f403c35d399d262544fa61a0c4879519125 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 18 May 2020 16:38:08 +0200 Subject: [PATCH] cpu/microwatt: update microwatt_wraper.vhdl --- litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl b/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl index 9ee82ece..4187ce4a 100644 --- a/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl +++ b/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl @@ -59,6 +59,8 @@ architecture rtl of microwatt_wrapper is signal wishbone_data_in : wishbone_slave_out; signal wishbone_data_out : wishbone_master_out; + signal xics_in : XicsToExecute1Type; + begin -- wishbone_insn mapping @@ -85,6 +87,9 @@ begin wishbone_data_sel <= wishbone_data_out.sel; wishbone_data_we <= wishbone_data_out.we; + -- xics_in mapping + xics_in.irq <= '0'; + microwatt_core : entity work.core generic map ( SIM => SIM, @@ -94,6 +99,8 @@ begin clk => clk, rst => rst, + alt_reset => '0', + wishbone_insn_in => wishbone_insn_in, wishbone_insn_out => wishbone_insn_out, @@ -107,6 +114,8 @@ begin dmi_wr => dmi_wr, dmi_ack => dmi_ack, + xics_in => xics_in, + terminated_out => terminated_out ); -- 2.30.2