From b538c6fbf231422395803f612ccfb17c7947710e Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Mon, 30 Mar 2020 18:08:25 +0000 Subject: [PATCH] Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung --- frontends/ast/ast.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 46801d691..24d6f56d8 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1458,20 +1458,24 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dictwire(intf.first) != nullptr) { + // Normally, removing wires would be batched together as it's an + // expensive operation, however, in this case doing so would mean + // that a cell with the same name cannot be created (below)... + // Since we won't expect many interfaces to exist in a module, + // we can let this slide... pool to_remove; to_remove.insert(mod->wire(intf.first)); mod->remove(to_remove); mod->fixup_ports(); - // We copy the cell of the interface to the sub-module such that it can further be found if it is propagated - // down to sub-sub-modules etc. - RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name); + // We copy the cell of the interface to the sub-module such that it + // can further be found if it is propagated down to sub-sub-modules etc. + RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name); new_subcell->set_bool_attribute("\\is_interface"); } else { log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str()); } } - mod->fixup_ports(); // If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module': if (interfaces.size() > 0) { -- 2.30.2