From b544d9f0568cad7082097d6d711d2ee0049c5a76 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 20:49:32 +0100 Subject: [PATCH] sigh. weirdness involving bit-inversion, inconsistency on mfcr and isel --- src/soc/fu/cr/test/test_pipe_caller.py | 2 ++ src/soc/simple/test/test_core.py | 22 ++++++++++++++++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 9fccbd2d..0a728a04 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -113,6 +113,8 @@ class CRTestCase(FHDLTestCase): initial_regs = [0] * 32 initial_regs[2] = random.randint(0, (1<<64)-1) initial_regs[3] = random.randint(0, (1<<64)-1) + #initial_regs[2] = i*2 + #initial_regs[3] = i*2+1 self.run_tst_program(Program(lst), initial_regs=initial_regs, initial_cr=cr) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 7fc77675..47d3e0d8 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -144,7 +144,7 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - sim = ISA(pdecode2, test.regs, test.sprs, 0) + sim = ISA(pdecode2, test.regs, test.sprs, test.cr) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) @@ -152,6 +152,20 @@ class TestRunner(FHDLTestCase): for i in range(32): yield core.regs.int.regs[i].reg.eq(test.regs[i]) + # set up CR regfile, "direct" write across all CRs + cr = test.cr + # sigh. Because POWER + cr = int('{:032b}'.format(test.cr)[::-1], 2) + print ("cr reg", hex(cr)) + for i in range(8): + j = i + cri = (cr>>(j*4)) & 0xf + # sigh. Because POWER + cri = int('{:04b}'.format(cri)[::-1], 2) + print ("cr reg", hex(cri), i, + core.regs.cr.regs[i].reg.shape()) + yield core.regs.cr.regs[i].reg.eq(cri) + # set up XER. "direct" write (bypass rd/write ports) xregs = core.regs.xer print ("sprs", test.sprs) @@ -221,9 +235,9 @@ if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() suite.addTest(TestRunner(CRTestCase.test_data)) - suite.addTest(TestRunner(ShiftRotTestCase.test_data)) - suite.addTest(TestRunner(LogicalTestCase.test_data)) - suite.addTest(TestRunner(ALUTestCase.test_data)) + #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) + #suite.addTest(TestRunner(LogicalTestCase.test_data)) + #suite.addTest(TestRunner(ALUTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2