From b54b3b336293e53984105f366a2832e2595cde68 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Jul 2020 07:53:42 +0200 Subject: [PATCH] interconnect/avalon: minor cleanup, remove max on SyncFIFO depth. --- litex/soc/interconnect/avalon.py | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/litex/soc/interconnect/avalon.py b/litex/soc/interconnect/avalon.py index dd6a4633..a14be66c 100644 --- a/litex/soc/interconnect/avalon.py +++ b/litex/soc/interconnect/avalon.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2019 Florent Kermarrec +# This file is Copyright (c) 2019-2020 Florent Kermarrec # License: BSD """Avalon support for LiteX""" @@ -19,7 +19,7 @@ from litex.soc.interconnect import stream class Native2AvalonST(Module): """Native LiteX's stream to Avalon-ST stream""" def __init__(self, layout, latency=2): - self.sink = sink = stream.Endpoint(layout) + self.sink = sink = stream.Endpoint(layout) self.source = source = stream.Endpoint(layout) # # # @@ -38,15 +38,13 @@ class Native2AvalonST(Module): class AvalonST2Native(Module): """Avalon-ST Stream to native LiteX's stream""" def __init__(self, layout, latency=2): - self.sink = sink = stream.Endpoint(layout) + self.sink = sink = stream.Endpoint(layout) self.source = source = stream.Endpoint(layout) # # # - buf = stream.SyncFIFO(layout, max(latency, 4)) + buf = stream.SyncFIFO(layout, latency) self.submodules += buf - self.comb += [ - sink.connect(buf.sink, omit={"ready"}), - sink.ready.eq(source.ready), - buf.source.connect(source) - ] + self.comb += sink.connect(buf.sink, omit={"ready"}) + self.comb += sink.ready.eq(source.ready) + self.comb += buf.source.connect(source) -- 2.30.2