From b5529992131d76d1d866358faaeb6c0fb2105851 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 5 Dec 2021 01:07:50 +0000 Subject: [PATCH] connect to dcache.bus standard interface when using wb_get --- src/openpower/test/runner.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index 51f4a596..2d6a825e 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -461,7 +461,8 @@ class TestRunnerBase(FHDLTestCase): if self.rom is not None: dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache default_mem = self.rom - sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE"))) + sim.add_sync_process(wrap(wb_get(dcache.bus, + default_mem, "DCACHE"))) with sim.write_vcd("issuer_simulator.vcd"): sim.run() -- 2.30.2