From b5621d633591e1283c5df07f7a937827d2ca4012 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Oct 2023 10:26:38 +0100
Subject: [PATCH] remove ambiguity of english description in stbsx

---
 openpower/isa/fixedstoreshift.mdwn  |   6 +-
 openpower/isa/pifixedloadshift.mdwn | 295 ++++++++++++++++++++++++++++
 2 files changed, 298 insertions(+), 3 deletions(-)
 create mode 100644 openpower/isa/pifixedloadshift.mdwn

diff --git a/openpower/isa/fixedstoreshift.mdwn b/openpower/isa/fixedstoreshift.mdwn
index c6d1f9b7..dbb22f03 100644
--- a/openpower/isa/fixedstoreshift.mdwn
+++ b/openpower/isa/fixedstoreshift.mdwn
@@ -28,9 +28,9 @@ Pseudo-code:
 
 Description:
 
-    Let the effective address (EA) be the sum (RA|0) plus the contents of
-    register RB shifted by (SH+1). RS [56:63] are stored into the byte in
-    storage addressed by EA.
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1) and (RA|0).
+    RS [56:63] are stored into the byte in storage addressed by EA.
 
 Special Registers Altered:
 
diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn
new file mode 100644
index 00000000..0418b1cd
--- /dev/null
+++ b/openpower/isa/pifixedloadshift.mdwn
@@ -0,0 +1,295 @@
+<!-- This defines DRAFT instructions that are to be proposed for SV -->
+
+<!-- This defines instructions that load from RAM to a register -->
+<!-- Effective Address is always RA, and the usual EA is stored late in RA -->
+
+<!-- Note that these pages also define equivalent store instructions, -->
+<!-- these are described in pifixedstore.mdwn -->
+
+
+
+# Load Byte and Zero with Post-Update
+
+D-Form
+
+* lbzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + EXTS(D)
+
+Description:
+
+    Let the effective address (EA) be register RA. 
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Byte and Zero with Post-Update Indexed
+
+X-Form
+
+* lbzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + (RB)
+
+Description:
+
+    Let the effective address (EA) be register RA.
+    The byte in storage addressed by EA is loaded into RT[56:63]. 
+    RT[0:55] are set to 0.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword and Zero with Post-Update
+
+D-Form
+
+* lhzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- (RA) + EXTS(D)
+
+Description:
+
+    Let the effective address (EA) be register RA. 
+    The halfword in storage addressed by EA is loaded into RT[48:63]. 
+    RT[0:47] are set to 0.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword and Zero with Post-Update Indexed
+
+X-Form
+
+* lhzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- (RA) + (RB)
+
+Description:
+
+    Let the effective address (EA) be register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63]. 
+    RT[0:47] are set to 0.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword Algebraic with Post-Update
+
+D-Form
+
+* lhaup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- (RA) + EXTS(D)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword Algebraic with Post-Update Indexed
+
+X-Form
+
+* lhaupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- (RA) + (RB)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Word and Zero with Post-Update
+
+D-Form
+
+* lwzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- [0]*32 || MEM(EA, 4)
+    RA <- (RA) + EXTS(D)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Word and Zero with Post-Update Indexed
+
+X-Form
+
+* lwzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- [0] * 32 || MEM(EA, 4)
+    RA <- (RA) + (RB)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Word Algebraic with Post-Update Indexed
+
+X-Form
+
+* lwaupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 4))
+    RA <- (RA) + (RB)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Doubleword with Post-Update Indexed
+
+DS-Form
+
+* ldup RT,DS(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- MEM(EA, 8)
+    RA <- (RA) + EXTS(DS || 0b00)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The doubleword in storage addressed by EA is loaded into RT.
+
+    The sum (RA)+ (DS||0b00) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Doubleword with Post-Update Indexed
+
+X-Form
+
+* ldupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- MEM(EA, 8)
+    RA <- (RA) + (RB)
+
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The doubleword in storage addressed by EA is loaded
+    into RT.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
-- 
2.30.2