From b57cba89a1d0a21fed88d0ecf5e259b063007240 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 18 May 2020 11:11:32 +0100 Subject: [PATCH] move countzero to fu/logical --- src/soc/fu/{countzero => logical}/countzero.py | 0 src/soc/fu/logical/main_stage.py | 2 +- src/soc/fu/{countzero => logical}/test/test_countzero.py | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename src/soc/fu/{countzero => logical}/countzero.py (100%) rename src/soc/fu/{countzero => logical}/test/test_countzero.py (98%) diff --git a/src/soc/fu/countzero/countzero.py b/src/soc/fu/logical/countzero.py similarity index 100% rename from src/soc/fu/countzero/countzero.py rename to src/soc/fu/logical/countzero.py diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index 06e1afbc..bb6efaf2 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -11,7 +11,7 @@ from soc.fu.logical.pipe_data import ALUInputData from soc.fu.alu.pipe_data import ALUOutputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp -from soc.fu.countzero.countzero import ZeroCounter +from soc.fu.logical.countzero import ZeroCounter from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange diff --git a/src/soc/fu/countzero/test/test_countzero.py b/src/soc/fu/logical/test/test_countzero.py similarity index 98% rename from src/soc/fu/countzero/test/test_countzero.py rename to src/soc/fu/logical/test/test_countzero.py index b795920c..43aae01d 100644 --- a/src/soc/fu/countzero/test/test_countzero.py +++ b/src/soc/fu/logical/test/test_countzero.py @@ -4,7 +4,7 @@ from nmigen.cli import rtlil from nmigen.back.pysim import Simulator, Delay from nmigen.test.utils import FHDLTestCase import unittest -from soc.fu.countzero.countzero import ZeroCounter +from soc.fu.logical.countzero import ZeroCounter class ZeroCounterTestCase(FHDLTestCase): -- 2.30.2