From b5bca267140bb75caa2206b14cf1c2154c64c61e Mon Sep 17 00:00:00 2001 From: isengaara Date: Wed, 15 Sep 2021 19:55:52 +0200 Subject: [PATCH] add new testcase for ompldst_multi using mmu --- .../test/test_compldst_multi_mmu.py | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 src/soc/experiment/test/test_compldst_multi_mmu.py diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py new file mode 100644 index 00000000..d6f82495 --- /dev/null +++ b/src/soc/experiment/test/test_compldst_multi_mmu.py @@ -0,0 +1,111 @@ +# test case for LOAD / STORE Computation Unit. + + +from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil +from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl +from nmigen.hdl.rec import Record, Layout + +""" +from nmutil.latch import SRLatch, latchregister +from nmutil.byterev import byte_reverse +from nmutil.extend import exts + +from soc.fu.regspec import RegSpecAPI + +from openpower.decoder.power_enums import MicrOp, Function, LDSTMode +from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset +from openpower.decoder.power_decoder2 import Data +from openpower.consts import MSR +""" + +from soc.experiment.compalu_multi import go_record, CompUnitRecord +from soc.experiment.l0_cache import PortInterface +from soc.experiment.pimem import LDSTException +from soc.experiment.compldst_multi import LDSTCompUnit +from soc.config.test.test_loadstore import TestMemPspec + +# for debugging +from nmutil.util import Display + +######################################## + +def ldst_sim(dut): + yield Display("TODO") + +######################################## + + +class TestLDSTCompUnitMMU(LDSTCompUnit): + + def __init__(self, rwid, pspec): + from soc.experiment.l0_cache import TstL0CacheBuffer + self.l0 = l0 = TstL0CacheBuffer(pspec) + pi = l0.l0.dports[0] + LDSTCompUnit.__init__(self, pi, rwid, 4) + + def elaborate(self, platform): + m = LDSTCompUnit.elaborate(self, platform) + m.submodules.l0 = self.l0 + # link addr-go direct to rel + m.d.comb += self.ad.go_i.eq(self.ad.rel_o) + return m + + +def test_scoreboard_mmu(): + + units = {} + pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb', + imem_ifacetype='bare_wb', + addr_wid=48, + mask_wid=8, + reg_wid=64, + units=units) + + dut = TestLDSTCompUnitMMU(16,pspec) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_ldst_comp_mmu1.il", "w") as f: + f.write(vl) + + run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd') + +######################################## +class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit): + + def __init__(self, pspec): + from soc.experiment.l0_cache import TstL0CacheBuffer + from soc.fu.ldst.pipe_data import LDSTPipeSpec + regspec = LDSTPipeSpec.regspec + self.l0 = l0 = TstL0CacheBuffer(pspec) + pi = l0.l0.dports[0] + LDSTCompUnit.__init__(self, pi, regspec, 4) + + def elaborate(self, platform): + m = LDSTCompUnit.elaborate(self, platform) + m.submodules.l0 = self.l0 + # link addr-go direct to rel + m.d.comb += self.ad.go_i.eq(self.ad.rel_o) + return m + + +def test_scoreboard_regspec_mmu(): + + units = {} + pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb', + imem_ifacetype='bare_wb', + addr_wid=48, + mask_wid=8, + reg_wid=64, + units=units) + + dut = TestLDSTCompUnitRegSpecMMU(pspec) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_ldst_comp_mmu2.il", "w") as f: + f.write(vl) + + run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd') + + +if __name__ == '__main__': + test_scoreboard_regspec_mmu() + #only one test for now -- test_scoreboard_mmu() -- 2.30.2