From b5d22a80fd03bdac1b5fcc7b6d26b6a72e81b500 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 13 Dec 2019 00:12:47 +0000 Subject: [PATCH] arch: Add generic BaseMMU MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This is an abstract class encapsulating the ITB and DTB (Instruction and Data TLBs) JIRA: https://gem5.atlassian.net/browse/GEM5-790 Change-Id: I7c8fa2ada319e631564182075da1aaff517ec212 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34975 Reviewed-by: Alexandru Duțu Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/ArmMMU.py | 46 ++++++++++++++ src/arch/arm/SConscript | 2 + src/arch/arm/mmu.cc | 44 ++++++++++++++ src/arch/arm/mmu.hh | 57 ++++++++++++++++++ src/arch/generic/BaseMMU.py | 47 +++++++++++++++ src/arch/generic/SConscript | 4 +- src/arch/generic/mmu.cc | 62 +++++++++++++++++++ src/arch/generic/mmu.hh | 116 ++++++++++++++++++++++++++++++++++++ src/arch/mips/MipsMMU.py | 46 ++++++++++++++ src/arch/mips/SConscript | 2 + src/arch/mips/mmu.cc | 44 ++++++++++++++ src/arch/mips/mmu.hh | 57 ++++++++++++++++++ src/arch/mips/tlb.cc | 2 +- src/arch/power/PowerMMU.py | 46 ++++++++++++++ src/arch/power/SConscript | 2 + src/arch/power/mmu.cc | 44 ++++++++++++++ src/arch/power/mmu.hh | 57 ++++++++++++++++++ src/arch/riscv/RiscvMMU.py | 46 ++++++++++++++ src/arch/riscv/SConscript | 2 + src/arch/riscv/mmu.cc | 44 ++++++++++++++ src/arch/riscv/mmu.hh | 57 ++++++++++++++++++ src/arch/sparc/SConscript | 2 + src/arch/sparc/SparcMMU.py | 48 +++++++++++++++ src/arch/sparc/mmu.cc | 44 ++++++++++++++ src/arch/sparc/mmu.hh | 57 ++++++++++++++++++ src/arch/x86/SConscript | 2 + src/arch/x86/X86MMU.py | 46 ++++++++++++++ src/arch/x86/mmu.cc | 44 ++++++++++++++ src/arch/x86/mmu.hh | 57 ++++++++++++++++++ 29 files changed, 1125 insertions(+), 2 deletions(-) create mode 100644 src/arch/arm/ArmMMU.py create mode 100644 src/arch/arm/mmu.cc create mode 100644 src/arch/arm/mmu.hh create mode 100644 src/arch/generic/BaseMMU.py create mode 100644 src/arch/generic/mmu.cc create mode 100644 src/arch/generic/mmu.hh create mode 100644 src/arch/mips/MipsMMU.py create mode 100644 src/arch/mips/mmu.cc create mode 100644 src/arch/mips/mmu.hh create mode 100644 src/arch/power/PowerMMU.py create mode 100644 src/arch/power/mmu.cc create mode 100644 src/arch/power/mmu.hh create mode 100644 src/arch/riscv/RiscvMMU.py create mode 100644 src/arch/riscv/mmu.cc create mode 100644 src/arch/riscv/mmu.hh create mode 100644 src/arch/sparc/SparcMMU.py create mode 100644 src/arch/sparc/mmu.cc create mode 100644 src/arch/sparc/mmu.hh create mode 100644 src/arch/x86/X86MMU.py create mode 100644 src/arch/x86/mmu.cc create mode 100644 src/arch/x86/mmu.hh diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py new file mode 100644 index 000000000..abd7d6064 --- /dev/null +++ b/src/arch/arm/ArmMMU.py @@ -0,0 +1,46 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.ArmTLB import ArmITB, ArmDTB +from m5.objects.BaseMMU import BaseMMU + +class ArmMMU(BaseMMU): + type = 'ArmMMU' + cxx_class = 'ArmISA::MMU' + cxx_header = 'arch/arm/mmu.hh' + itb = ArmITB() + dtb = ArmDTB() diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index e7781f6f5..fc2c3b284 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -81,6 +81,7 @@ if env['TARGET_ISA'] == 'arm': Source('freebsd/fs_workload.cc') Source('fs_workload.cc') Source('miscregs.cc') + Source('mmu.cc') Source('nativetrace.cc') Source('pauth_helpers.cc') Source('pmu.cc') @@ -100,6 +101,7 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmFsWorkload.py') SimObject('ArmInterrupts.py') SimObject('ArmISA.py') + SimObject('ArmMMU.py') SimObject('ArmNativeTrace.py') SimObject('ArmSemihosting.py') SimObject('ArmSystem.py') diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc new file mode 100644 index 000000000..504e0ac04 --- /dev/null +++ b/src/arch/arm/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/arm/mmu.hh" + +ArmISA::MMU * +ArmMMUParams::create() +{ + return new ArmISA::MMU(this); +} diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh new file mode 100644 index 000000000..6494f1f9d --- /dev/null +++ b/src/arch/arm/mmu.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ARM_MMU_HH__ +#define __ARCH_ARM_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/ArmMMU.hh" + +namespace ArmISA { + +class MMU : public BaseMMU +{ + public: + MMU(const ArmMMUParams *p) + : BaseMMU(p) + {} +}; + +} // namespace ArmISA + +#endif // __ARCH_ARM_MMU_HH__ diff --git a/src/arch/generic/BaseMMU.py b/src/arch/generic/BaseMMU.py new file mode 100644 index 000000000..77d6e08fc --- /dev/null +++ b/src/arch/generic/BaseMMU.py @@ -0,0 +1,47 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseTLB import BaseTLB +from m5.params import * +from m5.SimObject import SimObject + +class BaseMMU(SimObject): + type = 'BaseMMU' + abstract = True + cxx_header = "arch/generic/mmu.hh" + itb = Param.BaseTLB("Instruction TLB") + dtb = Param.BaseTLB("Data TLB") diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index 22654cda2..effb7c9fe 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -45,11 +45,13 @@ if env['TARGET_ISA'] == 'null': Source('decode_cache.cc') Source('decoder.cc') +Source('mmu.cc') +Source('pseudo_inst.cc') SimObject('BaseInterrupts.py') SimObject('BaseISA.py') +SimObject('BaseMMU.py') SimObject('BaseTLB.py') SimObject('ISACommon.py') DebugFlag('TLB') -Source('pseudo_inst.cc') diff --git a/src/arch/generic/mmu.cc b/src/arch/generic/mmu.cc new file mode 100644 index 000000000..4ef45fb0a --- /dev/null +++ b/src/arch/generic/mmu.cc @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * Copyright (c) 2011 Regents of the University of California + * Copyright (c) 2013 Advanced Micro Devices, Inc. + * Copyright (c) 2013 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/generic/mmu.hh" + +void +BaseMMU::takeOverFrom(BaseMMU *old_mmu) +{ + Port *old_itb_port = old_mmu->itb->getTableWalkerPort(); + Port *old_dtb_port = old_mmu->dtb->getTableWalkerPort(); + Port *new_itb_port = itb->getTableWalkerPort(); + Port *new_dtb_port = dtb->getTableWalkerPort(); + + // Move over any table walker ports if they exist + if (new_itb_port) + new_itb_port->takeOverFrom(old_itb_port); + if (new_dtb_port) + new_dtb_port->takeOverFrom(old_dtb_port); + + itb->takeOverFrom(old_mmu->itb); + dtb->takeOverFrom(old_mmu->dtb); +} diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh new file mode 100644 index 000000000..fd1eb2f71 --- /dev/null +++ b/src/arch/generic/mmu.hh @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_GENERIC_MMU_HH__ +#define __ARCH_GENERIC_MMU_HH__ + +#include "arch/generic/tlb.hh" + +#include "params/BaseMMU.hh" + +class BaseMMU : public SimObject +{ + protected: + typedef BaseMMUParams Params; + + BaseMMU(const Params *p) + : SimObject(p), dtb(p->dtb), itb(p->itb) + {} + + public: + void + flushAll() + { + dtb->flushAll(); + itb->flushAll(); + } + + void + demapPage(Addr vaddr, uint64_t asn) + { + itb->demapPage(vaddr, asn); + dtb->demapPage(vaddr, asn); + } + + Fault + translateAtomic(const RequestPtr &req, ThreadContext *tc, + BaseTLB::Mode mode) + { + if (mode == BaseTLB::Execute) + return itb->translateAtomic(req, tc, mode); + else + return dtb->translateAtomic(req, tc, mode); + } + + void + translateTiming(const RequestPtr &req, ThreadContext *tc, + BaseTLB::Translation *translation, BaseTLB::Mode mode) + { + if (mode == BaseTLB::Execute) + return itb->translateTiming(req, tc, translation, mode); + else + return dtb->translateTiming(req, tc, translation, mode); + } + + Fault + translateFunctional(const RequestPtr &req, ThreadContext *tc, + BaseTLB::Mode mode) + { + if (mode == BaseTLB::Execute) + return itb->translateFunctional(req, tc, mode); + else + return dtb->translateFunctional(req, tc, mode); + } + + Fault + finalizePhysical(const RequestPtr &req, ThreadContext *tc, + BaseTLB::Mode mode) const + { + if (mode == BaseTLB::Execute) + return itb->finalizePhysical(req, tc, mode); + else + return dtb->finalizePhysical(req, tc, mode); + } + + void takeOverFrom(BaseMMU *old_mmu); + + public: + BaseTLB* dtb; + BaseTLB* itb; +}; + +#endif diff --git a/src/arch/mips/MipsMMU.py b/src/arch/mips/MipsMMU.py new file mode 100644 index 000000000..e6dcd979a --- /dev/null +++ b/src/arch/mips/MipsMMU.py @@ -0,0 +1,46 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseMMU import BaseMMU +from m5.objects.MipsTLB import MipsTLB + +class MipsMMU(BaseMMU): + type = 'MipsMMU' + cxx_class = 'MipsISA::MMU' + cxx_header = 'arch/mips/mmu.hh' + itb = MipsTLB() + dtb = MipsTLB() diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index d8771de8c..9b5f6e40b 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -38,6 +38,7 @@ if env['TARGET_ISA'] == 'mips': Source('isa.cc') Source('linux/linux.cc') Source('linux/process.cc') + Source('mmu.cc') Source('pagetable.cc') Source('process.cc') Source('remote_gdb.cc') @@ -46,6 +47,7 @@ if env['TARGET_ISA'] == 'mips': SimObject('MipsInterrupts.py') SimObject('MipsISA.py') + SimObject('MipsMMU.py') SimObject('MipsTLB.py') DebugFlag('MipsPRA') diff --git a/src/arch/mips/mmu.cc b/src/arch/mips/mmu.cc new file mode 100644 index 000000000..ea405fa7b --- /dev/null +++ b/src/arch/mips/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/mmu.hh" + +MipsISA::MMU * +MipsMMUParams::create() +{ + return new MipsISA::MMU(this); +} diff --git a/src/arch/mips/mmu.hh b/src/arch/mips/mmu.hh new file mode 100644 index 000000000..ea8369fd1 --- /dev/null +++ b/src/arch/mips/mmu.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 MIPS Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_MMU_HH__ +#define __ARCH_MIPS_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/MipsMMU.hh" + +namespace MipsISA { + +class MMU : public BaseMMU +{ + public: + MMU(const MipsMMUParams *p) + : BaseMMU(p) + {} +}; + +} // namespace MipsISA + +#endif // __ARCH_MIPS_MMU_HH__ diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 49092ef6f..931e09a5c 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -261,5 +261,5 @@ TLB::index(bool advance) MipsISA::TLB * MipsTLBParams::create() { - return new TLB(this); + return new MipsISA::TLB(this); } diff --git a/src/arch/power/PowerMMU.py b/src/arch/power/PowerMMU.py new file mode 100644 index 000000000..1d966bb7b --- /dev/null +++ b/src/arch/power/PowerMMU.py @@ -0,0 +1,46 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseMMU import BaseMMU +from m5.objects.PowerTLB import PowerTLB + +class PowerMMU(BaseMMU): + type = 'PowerMMU' + cxx_class = 'PowerISA::MMU' + cxx_header = 'arch/power/mmu.hh' + itb = PowerTLB() + dtb = PowerTLB() diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index 1187acf3d..1df33d381 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -43,6 +43,7 @@ if env['TARGET_ISA'] == 'power': Source('interrupts.cc') Source('linux/linux.cc') Source('linux/process.cc') + Source('mmu.cc') Source('isa.cc') Source('pagetable.cc') Source('process.cc') @@ -52,6 +53,7 @@ if env['TARGET_ISA'] == 'power': SimObject('PowerInterrupts.py') SimObject('PowerISA.py') + SimObject('PowerMMU.py') SimObject('PowerTLB.py') DebugFlag('Power') diff --git a/src/arch/power/mmu.cc b/src/arch/power/mmu.cc new file mode 100644 index 000000000..cda2f299d --- /dev/null +++ b/src/arch/power/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/power/mmu.hh" + +PowerISA::MMU * +PowerMMUParams::create() +{ + return new PowerISA::MMU(this); +} diff --git a/src/arch/power/mmu.hh b/src/arch/power/mmu.hh new file mode 100644 index 000000000..127299f4d --- /dev/null +++ b/src/arch/power/mmu.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_POWER_MMU_HH__ +#define __ARCH_POWER_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/PowerMMU.hh" + +namespace PowerISA { + +class MMU : public BaseMMU +{ + public: + MMU(const PowerMMUParams *p) + : BaseMMU(p) + {} +}; + +} // namespace PowerISA + +#endif // __ARCH_POWER_MMU_HH__ diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py new file mode 100644 index 000000000..4b45b28c1 --- /dev/null +++ b/src/arch/riscv/RiscvMMU.py @@ -0,0 +1,46 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseMMU import BaseMMU +from m5.objects.RiscvTLB import RiscvTLB + +class RiscvMMU(BaseMMU): + type = 'RiscvMMU' + cxx_class = 'RiscvISA::MMU' + cxx_header = 'arch/riscv/mmu.hh' + itb = RiscvTLB() + dtb = RiscvTLB() diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript index f99152097..3fddd3123 100644 --- a/src/arch/riscv/SConscript +++ b/src/arch/riscv/SConscript @@ -48,6 +48,7 @@ if env['TARGET_ISA'] == 'riscv': Source('isa.cc') Source('interrupts.cc') Source('locked_mem.cc') + Source('mmu.cc') Source('process.cc') Source('pagetable.cc') Source('pagetable_walker.cc') @@ -62,6 +63,7 @@ if env['TARGET_ISA'] == 'riscv': SimObject('RiscvFsWorkload.py') SimObject('RiscvInterrupts.py') SimObject('RiscvISA.py') + SimObject('RiscvMMU.py') SimObject('RiscvTLB.py') DebugFlag('RiscvMisc') diff --git a/src/arch/riscv/mmu.cc b/src/arch/riscv/mmu.cc new file mode 100644 index 000000000..6aba56035 --- /dev/null +++ b/src/arch/riscv/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/riscv/mmu.hh" + +RiscvISA::MMU * +RiscvMMUParams::create() +{ + return new RiscvISA::MMU(this); +} diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh new file mode 100644 index 000000000..361aa0870 --- /dev/null +++ b/src/arch/riscv/mmu.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_RISCV_MMU_HH__ +#define __ARCH_RISCV_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/RiscvMMU.hh" + +namespace RiscvISA { + +class MMU : public BaseMMU +{ + public: + MMU(const RiscvMMUParams *p) + : BaseMMU(p) + {} +}; + +} // namespace RiscvISA + +#endif // __ARCH_RISCV_MMU_HH__ diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index c7d094030..4c855ba4d 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -38,6 +38,7 @@ if env['TARGET_ISA'] == 'sparc': Source('linux/linux.cc') Source('linux/process.cc') Source('linux/syscalls.cc') + Source('mmu.cc') Source('nativetrace.cc') Source('pagetable.cc') Source('process.cc') @@ -51,6 +52,7 @@ if env['TARGET_ISA'] == 'sparc': SimObject('SparcFsWorkload.py') SimObject('SparcInterrupts.py') SimObject('SparcISA.py') + SimObject('SparcMMU.py') SimObject('SparcNativeTrace.py') SimObject('SparcTLB.py') diff --git a/src/arch/sparc/SparcMMU.py b/src/arch/sparc/SparcMMU.py new file mode 100644 index 000000000..16f98f8c9 --- /dev/null +++ b/src/arch/sparc/SparcMMU.py @@ -0,0 +1,48 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.SimObject import SimObject +from m5.params import * +from m5.objects.BaseMMU import BaseMMU +from m5.objects.SparcTLB import SparcTLB + +class SparcMMU(BaseMMU): + type = 'SparcMMU' + cxx_class = 'SparcISA::MMU' + cxx_header = 'arch/sparc/mmu.hh' + itb = SparcTLB() + dtb = SparcTLB() diff --git a/src/arch/sparc/mmu.cc b/src/arch/sparc/mmu.cc new file mode 100644 index 000000000..525d2acd3 --- /dev/null +++ b/src/arch/sparc/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/sparc/mmu.hh" + +SparcISA::MMU * +SparcMMUParams::create() +{ + return new SparcISA::MMU(this); +} diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh new file mode 100644 index 000000000..915a61444 --- /dev/null +++ b/src/arch/sparc/mmu.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_SPARC_MMU_HH__ +#define __ARCH_SPARC_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/SparcMMU.hh" + +namespace SparcISA { + +class MMU : public BaseMMU +{ + public: + MMU(const SparcMMUParams *p) + : BaseMMU(p) + {} +}; + +} // namespace SparcISA + +#endif // __ARCH_SPARC_MMU_HH__ diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 1be41ed7a..828fcc97c 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -59,6 +59,7 @@ if env['TARGET_ISA'] == 'x86': Source('linux/fs_workload.cc') Source('linux/linux.cc') Source('linux/process.cc') + Source('mmu.cc') Source('nativetrace.cc') Source('pagetable.cc') Source('pagetable_walker.cc') @@ -72,6 +73,7 @@ if env['TARGET_ISA'] == 'x86': SimObject('X86FsWorkload.py') SimObject('X86ISA.py') SimObject('X86LocalApic.py') + SimObject('X86MMU.py') SimObject('X86NativeTrace.py') SimObject('X86TLB.py') diff --git a/src/arch/x86/X86MMU.py b/src/arch/x86/X86MMU.py new file mode 100644 index 000000000..ee30b5fbd --- /dev/null +++ b/src/arch/x86/X86MMU.py @@ -0,0 +1,46 @@ +# -*- mode:python -*- + +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseMMU import BaseMMU +from m5.objects.X86TLB import X86TLB + +class X86MMU(BaseMMU): + type = 'X86MMU' + cxx_class = 'X86ISA::MMU' + cxx_header = 'arch/x86/mmu.hh' + itb = X86TLB() + dtb = X86TLB() diff --git a/src/arch/x86/mmu.cc b/src/arch/x86/mmu.cc new file mode 100644 index 000000000..efaf620d8 --- /dev/null +++ b/src/arch/x86/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/x86/mmu.hh" + +X86ISA::MMU * +X86MMUParams::create() +{ + return new X86ISA::MMU(this); +} diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh new file mode 100644 index 000000000..6f4ba8775 --- /dev/null +++ b/src/arch/x86/mmu.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_X86_MMU_HH__ +#define __ARCH_X86_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/X86MMU.hh" + +namespace X86ISA { + +class MMU : public BaseMMU +{ + public: + MMU(const X86MMUParams *p) + : BaseMMU(p) + {} +}; + +} // namespace X86ISA + +#endif // __ARCH_X86_MMU_HH__ -- 2.30.2