From b5eab453ff91429a6629a7245f8dd08657618b21 Mon Sep 17 00:00:00 2001 From: Ken Raeburn Date: Fri, 20 Oct 1995 22:22:07 +0000 Subject: [PATCH] update copyrights --- include/opcode/hppa.h | 526 +++++++++++++++++++++--------------------- include/opcode/mips.h | 28 ++- 2 files changed, 282 insertions(+), 272 deletions(-) diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index eef20fc8a90..4d1728ae0fc 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -1,5 +1,5 @@ /* Table of opcodes for the PA-RISC. - Copyright (C) 1990, 1991, 1993 Free Software Foundation, Inc. + Copyright (C) 1990, 1991, 1993, 1995 Free Software Foundation, Inc. Contributed by the Center for Software Science at the University of Utah (pa-gdb-bugs@cs.utah.edu). @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GAS or GDB; see the file COPYING. If not, write to -the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #if !defined(__STDC__) && !defined(const) #define const @@ -36,18 +36,13 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ * #undef it away. */ #undef NONE -enum delay_type {NONE, NORMAL, CONDITIONAL}; struct pa_opcode { const char *name; unsigned long int match; /* Bits that must be set... */ unsigned long int mask; /* ... in these bits. */ char *args; - /* Nonzero if this is a delayed branch instruction. */ - /* What uses this field? Nothing in opcodes or gas that I saw. - If nothing needs it, we could reduce this table by 20% (for - most machines). KR */ - char delayed; + enum pa_arch arch; }; /* @@ -69,7 +64,7 @@ struct pa_opcode In the args field, the following characters are unused: - ' "#$% *+- ./ 3 :; = @' + ' "#$% *+- ./ 3 :; = ' ' B L [\] _' ' e gh lm qr { } ' @@ -134,7 +129,8 @@ Also these: (for 0xe format FP instructions) G Destination Floating Point Operand Format Completer encoded 2 bits at 18 M Floating-Point Compare Conditions (encoded as 5 bits at 31) - ? negated compare/subtract conditions. + ? non-negated/negated compare/subtract conditions. + @ non-negated/negated add conditions. ! non-negated add conditions. s 2 bit space specifier at 17. @@ -177,286 +173,286 @@ static const struct pa_opcode pa_opcodes[] = /* pseudo-instructions */ -{ "b", 0xe8000000, 0xffe0e000, "nW", NORMAL}, /* bl foo,r0 */ -{ "ldi", 0x34000000, 0xffe0c000, "j,x"}, /* ldo val(r0),r */ -{ "comib", 0x84000000, 0xfc000000, "?n5,b,w", CONDITIONAL}, /* comib{tf}*/ -{ "comb", 0x80000000, 0xfc000000, "?nx,b,w", CONDITIONAL}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL}, /* addb{tf} */ -{ "addib", 0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL}, /* addib{tf}*/ -{ "nop", 0x08000240, 0xffffffff, ""}, /* or 0,0,0 */ -{ "copy", 0x08000240, 0xffe0ffe0, "x,t"}, /* or r,0,t */ -{ "mtsar", 0x01601840, 0xffe0ffff, "x"}, /* mtctl r,cr11 */ +{ "b", 0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */ +{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10}, /* ldo val(r0),r */ +{ "comib", 0x84000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/ +{ "comb", 0x80000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */ +{ "addb", 0xa0000000, 0xfc000000, "@nx,b,w", pa10}, /* addb{tf} */ +{ "addib", 0xa4000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/ +{ "nop", 0x08000240, 0xffffffff, "", pa10}, /* or 0,0,0 */ +{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10}, /* or r,0,t */ +{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */ /* Loads and Stores for integer registers. */ -{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x"}, -{ "ldw", 0x48000000, 0xfc000000, "j(b),x"}, -{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x"}, -{ "ldh", 0x44000000, 0xfc000000, "j(b),x"}, -{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x"}, -{ "ldb", 0x40000000, 0xfc000000, "j(b),x"}, -{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)"}, -{ "stw", 0x68000000, 0xfc000000, "x,j(b)"}, -{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)"}, -{ "sth", 0x64000000, 0xfc000000, "x,j(b)"}, -{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)"}, -{ "stb", 0x60000000, 0xfc000000, "x,j(b)"}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x"}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x"}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)"}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)"}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(s,b),t"}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(b),t"}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(s,b),t"}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(b),t"}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(s,b),t"}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(b),t"}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t"}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(s,b),t"}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(b),t"}, -{ "ldws", 0x0c001080, 0xfc001fc0, "C5(s,b),t"}, -{ "ldws", 0x0c001080, 0xfc001fc0, "C5(b),t"}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(s,b),t"}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(b),t"}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(s,b),t"}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(b),t"}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t"}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(s,b),t"}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(b),t"}, -{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(s,b)"}, -{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(b)"}, -{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(s,b)"}, -{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(b)"}, -{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(s,b)"}, -{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(b)"}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "Cx,V(b)"}, -{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(s,b)"}, -{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(b)"}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10}, +{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10}, +{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10}, +{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10}, +{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10}, +{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10}, +{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10}, +{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10}, +{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10}, +{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10}, +{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10}, +{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(s,b),t", pa10}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(b),t", pa10}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(s,b),t", pa10}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(b),t", pa10}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(s,b),t", pa10}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(b),t", pa10}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t", pa10}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(s,b),t", pa10}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(b),t", pa10}, +{ "ldws", 0x0c001080, 0xfc001fc0, "C5(s,b),t", pa10}, +{ "ldws", 0x0c001080, 0xfc001fc0, "C5(b),t", pa10}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(s,b),t", pa10}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(b),t", pa10}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(s,b),t", pa10}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(b),t", pa10}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t", pa10}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(s,b),t", pa10}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(b),t", pa10}, +{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(s,b)", pa10}, +{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(b)", pa10}, +{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(s,b)", pa10}, +{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(b)", pa10}, +{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(s,b)", pa10}, +{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(b)", pa10}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "Cx,V(b)", pa10}, +{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(s,b)", pa10}, +{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(b)", pa10}, /* Immediate instructions. */ -{ "ldo", 0x34000000, 0xfc00c000, "j(b),x"}, -{ "ldil", 0x20000000, 0xfc000000, "k,b"}, -{ "addil", 0x28000000, 0xfc000000, "k,b"}, +{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10}, +{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10}, +{ "addil", 0x28000000, 0xfc000000, "k,b", pa10}, /* Branching instructions. */ -{ "bl", 0xe8000000, 0xfc00e000, "nW,b", NORMAL}, -{ "gate", 0xe8002000, 0xfc00e000, "nW,b", NORMAL}, -{ "blr", 0xe8004000, 0xfc00e001, "nx,b", NORMAL}, -{ "bv", 0xe800c000, 0xfc00e001, "nx(b)", NORMAL}, -{ "bv", 0xe800c000, 0xfc00e001, "n(b)", NORMAL}, -{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", NORMAL}, -{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", NORMAL}, -{ "movb", 0xc8000000, 0xfc000000, "|nx,b,w", CONDITIONAL}, -{ "movib", 0xcc000000, 0xfc000000, "|n5,b,w", CONDITIONAL}, -{ "combt", 0x80000000, 0xfc000000, "x,b,t", CONDITIONAL}, -{ "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", CONDITIONAL}, -{ "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", CONDITIONAL}, -{ "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", CONDITIONAL}, -{ "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", CONDITIONAL}, -{ "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", CONDITIONAL}, -{ "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", CONDITIONAL}, -{ "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", CONDITIONAL}, -{ "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", CONDITIONAL}, -{ "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", CONDITIONAL}, -{ "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", CONDITIONAL}, -{ "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", CONDITIONAL}, -{ "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", CONDITIONAL}, -{ "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", CONDITIONAL}, +{ "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", pa10}, +{ "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", pa10}, +{ "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", pa10}, +{ "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", pa10}, +{ "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", pa10}, +{ "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", pa10}, +{ "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", pa10}, +{ "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", pa10}, +{ "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", pa10}, +{ "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", pa10}, +{ "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", pa10}, +{ "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", pa10}, +{ "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", pa10}, +{ "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", pa10}, /* System Control Instructions */ -{ "break", 0x00000000, 0xfc001fe0, "r,A"}, -{ "rfi", 0x00000c00, 0xffffffff, ""}, -{ "rfir", 0x00000ca0, 0xffffffff, ""}, -{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t"}, -{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t"}, -{ "mtsm", 0x00001860, 0xffe0ffff, "x"}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t"}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t"}, -{ "mtsp", 0x00001820, 0xffe01fff, "x,S"}, -{ "mtctl", 0x00001840, 0xfc00ffff, "x,^"}, -{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t"}, -{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t"}, -{ "sync", 0x00000400, 0xffffffff, ""}, -{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t"}, -{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t"}, -{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t"}, -{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t"}, -{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t"}, -{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t"}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t"}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t"}, -{ "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t"}, -{ "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t"}, -{ "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t"}, -{ "lha", 0x04001300, 0xfc003fc0, "Zx(b),t"}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(s,b)"}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(b)"}, -{ "pitlb", 0x04000200, 0xfc003fdf, "Zx(s,b)"}, -{ "pitlb", 0x04000200, 0xfc003fdf, "Zx(b)"}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(s,b)"}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(b)"}, -{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(s,b)"}, -{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(b)"}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)"}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)"}, -{ "iitlba", 0x04000040, 0xfc003fff, "x,(s,b)"}, -{ "iitlba", 0x04000040, 0xfc003fff, "x,(b)"}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)"}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)"}, -{ "iitlbp", 0x04000000, 0xfc003fff, "x,(s,b)"}, -{ "iitlbp", 0x04000000, 0xfc003fff, "x,(b)"}, -{ "pdc", 0x04001380, 0xfc003fdf, "Zx(s,b)"}, -{ "pdc", 0x04001380, 0xfc003fdf, "Zx(b)"}, -{ "fdc", 0x04001280, 0xfc003fdf, "Zx(s,b)"}, -{ "fdc", 0x04001280, 0xfc003fdf, "Zx(b)"}, -{ "fic", 0x04000280, 0xfc003fdf, "Zx(s,b)"}, -{ "fic", 0x04000280, 0xfc003fdf, "Zx(b)"}, -{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(s,b)"}, -{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(b)"}, -{ "fice", 0x040002c0, 0xfc003fdf, "Zx(s,b)"}, -{ "fice", 0x040002c0, 0xfc003fdf, "Zx(b)"}, -{ "diag", 0x14000000, 0xfc000000, "D"}, +{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10}, +{ "rfi", 0x00000c00, 0xffffffff, "", pa10}, +{ "rfir", 0x00000ca0, 0xffffffff, "", pa11}, +{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10}, +{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10}, +{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10}, +{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10}, +{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10}, +{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10}, +{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10}, +{ "sync", 0x00000400, 0xffffffff, "", pa10}, +{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10}, +{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10}, +{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10}, +{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10}, +{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10}, +{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10}, +{ "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t", pa10}, +{ "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t", pa10}, +{ "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t", pa10}, +{ "lha", 0x04001300, 0xfc003fc0, "Zx(b),t", pa10}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(b)", pa10}, +{ "pitlb", 0x04000200, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "pitlb", 0x04000200, 0xfc003fdf, "Zx(b)", pa10}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(b)", pa10}, +{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "pitlbe", 0x04000240, 0xfc003fdf, "Zx(b)", pa10}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10}, +{ "iitlba", 0x04000040, 0xfc003fff, "x,(s,b)", pa10}, +{ "iitlba", 0x04000040, 0xfc003fff, "x,(b)", pa10}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10}, +{ "iitlbp", 0x04000000, 0xfc003fff, "x,(s,b)", pa10}, +{ "iitlbp", 0x04000000, 0xfc003fff, "x,(b)", pa10}, +{ "pdc", 0x04001380, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "pdc", 0x04001380, 0xfc003fdf, "Zx(b)", pa10}, +{ "fdc", 0x04001280, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "fdc", 0x04001280, 0xfc003fdf, "Zx(b)", pa10}, +{ "fic", 0x04000280, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "fic", 0x04000280, 0xfc003fdf, "Zx(b)", pa10}, +{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(b)", pa10}, +{ "fice", 0x040002c0, 0xfc003fdf, "Zx(s,b)", pa10}, +{ "fice", 0x040002c0, 0xfc003fdf, "Zx(b)", pa10}, +{ "diag", 0x14000000, 0xfc000000, "D", pa10}, /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ -{ "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)"}, -{ "gfw", 0x04001680, 0xfc003fdf, "Zx(b)"}, -{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)"}, -{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(b)"}, +{ "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)", pa11}, +{ "gfw", 0x04001680, 0xfc003fdf, "Zx(b)", pa11}, +{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)", pa11}, +{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(b)", pa11}, /* Floating Point Coprocessor Instructions */ -{ "fldwx", 0x24000000, 0xfc001f80, "cx(s,b),v"}, -{ "fldwx", 0x24000000, 0xfc001f80, "cx(b),v"}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cx(s,b),y"}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cx(b),y"}, -{ "fstwx", 0x24000200, 0xfc001fc0, "cv,x(s,b)"}, -{ "fstwx", 0x24000200, 0xfc001fc0, "cv,x(b)"}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)"}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)"}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)"}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)"}, -{ "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v"}, -{ "fldws", 0x24001000, 0xfc001f80, "C5(b),v"}, -{ "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y"}, -{ "fldds", 0x2c001000, 0xfc001fc0, "C5(b),y"}, -{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(s,b)"}, -{ "fstws", 0x24001200, 0xfc001f80, "Cy,5(b)"}, -{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)"}, -{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)"}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)"}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)"}, -{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v"}, -{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v"}, -{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v"}, -{ "fsub", 0x38002600, 0xfc00e720, "IJ,K,v"}, -{ "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v"}, -{ "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v"}, -{ "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v"}, -{ "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v"}, -{ "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v"}, -{ "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v"}, -{ "fabs", 0x30006000, 0xfc1fe7e0, "FE,v"}, -{ "fabs", 0x38006000, 0xfc1fe720, "FJ,v"}, -{ "frem", 0x30008600, 0xfc00e7e0, "FE,X,v"}, -{ "frem", 0x38008600, 0xfc00e720, "FJ,K,v"}, -{ "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v"}, -{ "frnd", 0x3800a000, 0xfc1fe720, "FJ,v"}, -{ "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v"}, -{ "fcpy", 0x38004000, 0xfc1fe720, "FJ,v"}, -{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v"}, -{ "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v"}, -{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v"}, -{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v"}, -{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v"}, -{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v"}, -{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v"}, -{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v"}, -{ "fcmp", 0x30000400, 0xfc00e7e0, "FME,X"}, -{ "fcmp", 0x38000400, 0xfc00e720, "IMJ,K"}, -{ "xmpyu", 0x38004700, 0xfc00e720, "E,X,v"}, -{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8"}, -{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8"}, -{ "ftest", 0x30002420, 0xffffffff, ""}, +{ "fldwx", 0x24000000, 0xfc001f80, "cx(s,b),v", pa10}, +{ "fldwx", 0x24000000, 0xfc001f80, "cx(b),v", pa10}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cx(s,b),y", pa10}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cx(b),y", pa10}, +{ "fstwx", 0x24000200, 0xfc001f80, "cv,x(s,b)", pa10}, +{ "fstwx", 0x24000200, 0xfc001f80, "cv,x(b)", pa10}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)", pa10}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)", pa10}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)", pa10}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)", pa10}, +{ "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v", pa10}, +{ "fldws", 0x24001000, 0xfc001f80, "C5(b),v", pa10}, +{ "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y", pa10}, +{ "fldds", 0x2c001000, 0xfc001fc0, "C5(b),y", pa10}, +{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(s,b)", pa10}, +{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(b)", pa10}, +{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)", pa10}, +{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)", pa10}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)", pa10}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)", pa10}, +{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v", pa10}, +{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v", pa10}, +{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v", pa10}, +{ "fsub", 0x38002600, 0xfc00e720, "IJ,K,v", pa10}, +{ "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v", pa10}, +{ "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v", pa10}, +{ "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v", pa10}, +{ "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v", pa10}, +{ "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v", pa10}, +{ "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v", pa10}, +{ "fabs", 0x30006000, 0xfc1fe7e0, "FE,v", pa10}, +{ "fabs", 0x38006000, 0xfc1fe720, "FJ,v", pa10}, +{ "frem", 0x30008600, 0xfc00e7e0, "FE,X,v", pa10}, +{ "frem", 0x38008600, 0xfc00e720, "FJ,K,v", pa10}, +{ "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v", pa10}, +{ "frnd", 0x3800a000, 0xfc1fe720, "FJ,v", pa10}, +{ "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v", pa10}, +{ "fcpy", 0x38004000, 0xfc1fe720, "FJ,v", pa10}, +{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v", pa10}, +{ "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v", pa10}, +{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v", pa10}, +{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v", pa10}, +{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v", pa10}, +{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v", pa10}, +{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v", pa10}, +{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v", pa10}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "FME,X", pa10}, +{ "fcmp", 0x38000400, 0xfc00e720, "IMJ,K", pa10}, +{ "xmpyu", 0x38004700, 0xfc00e720, "E,X,v", pa11}, +{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8", pa11}, +{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8", pa11}, +{ "ftest", 0x30002420, 0xffffffff, "", pa10}, /* Assist Instructions */ -{ "spop0", 0x10000000, 0xfc000600, "f,ON", NORMAL}, -{ "spop1", 0x10000200, 0xfc000600, "f,oNt", NORMAL}, -{ "spop2", 0x10000400, 0xfc000600, "f,1Nb", NORMAL}, -{ "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", NORMAL}, -{ "copr", 0x30000000, 0xfc000000, "u,2N", NORMAL}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucx(s,b),t"}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucx(b),t"}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucx(s,b),t"}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucx(b),t"}, -{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(s,b)"}, -{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(b)"}, -{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(s,b)"}, -{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(b)"}, -{ "cldws", 0x24001000, 0xfc001e00, "uC5(s,b),t"}, -{ "cldws", 0x24001000, 0xfc001e00, "uC5(b),t"}, -{ "cldds", 0x2c001000, 0xfc001e00, "uC5(s,b),t"}, -{ "cldds", 0x2c001000, 0xfc001e00, "uC5(b),t"}, -{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(s,b)"}, -{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(b)"}, -{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(s,b)"}, -{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(b)"}, +{ "spop0", 0x10000000, 0xfc000600, "f,ON", pa10}, +{ "spop1", 0x10000200, 0xfc000600, "f,oNt", pa10}, +{ "spop2", 0x10000400, 0xfc000600, "f,1Nb", pa10}, +{ "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", pa10}, +{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucx(s,b),t", pa10}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucx(b),t", pa10}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucx(s,b),t", pa10}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucx(b),t", pa10}, +{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(s,b)", pa10}, +{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(b)", pa10}, +{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(s,b)", pa10}, +{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(b)", pa10}, +{ "cldws", 0x24001000, 0xfc001e00, "uC5(s,b),t", pa10}, +{ "cldws", 0x24001000, 0xfc001e00, "uC5(b),t", pa10}, +{ "cldds", 0x2c001000, 0xfc001e00, "uC5(s,b),t", pa10}, +{ "cldds", 0x2c001000, 0xfc001e00, "uC5(b),t", pa10}, +{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(s,b)", pa10}, +{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(b)", pa10}, +{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(s,b)", pa10}, +{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(b)", pa10}, }; #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 366e2430489..b65d791e8d5 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1,5 +1,5 @@ /* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993 Free Software Foundation, Inc. + Copyright 1993, 1995 Free Software Foundation, Inc. Contributed by Ralph Campbell and OSF Commented and modified by Ian Lance Taylor, Cygnus Support @@ -17,7 +17,7 @@ the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* These are bit masks and shift counts to use to access the various fields of an instruction. To retrieve the X field of an @@ -54,8 +54,12 @@ Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define OP_SH_OP 26 #define OP_MASK_RS 0x1f #define OP_SH_RS 21 +#define OP_MASK_FR 0x1f +#define OP_SH_FR 21 #define OP_MASK_FMT 0x1f #define OP_SH_FMT 21 +#define OP_MASK_BCC 0x7 +#define OP_SH_BCC 18 #define OP_MASK_CODE 0x3ff #define OP_SH_CODE 16 #define OP_MASK_RT 0x1f @@ -68,6 +72,10 @@ Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define OP_SH_RD 11 #define OP_MASK_FS 0x1f #define OP_SH_FS 11 +#define OP_MASK_PREFX 0x1f +#define OP_SH_PREFX 11 +#define OP_MASK_CCC 0x7 +#define OP_SH_CCC 8 #define OP_MASK_SYSCALL 0xfffff #define OP_SH_SYSCALL 6 #define OP_MASK_SHAMT 0x1f @@ -127,6 +135,7 @@ struct mips_opcode "b" 5 bit base register (OP_*_RS) "c" 10 bit breakpoint code (OP_*_CODE) "d" 5 bit destination register specifier (OP_*_RD) + "h" 5 bit prefx hint (OP_*_PREFX) "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) @@ -145,8 +154,11 @@ struct mips_opcode Floating point instructions: "D" 5 bit destination register (OP_*_FD) + "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) + "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) "S" 5 bit fs source 1 register (OP_*_FS) "T" 5 bit ft source 2 register (OP_*_FT) + "R" 5 bit fr source 3 register (OP_*_FR) "V" 5 bit same register used as floating source and destination (OP_*_FS) "W" 5 bit same register used as floating target and destination (OP_*_FT) @@ -186,14 +198,14 @@ struct mips_opcode #define INSN_READ_FPR_S 0x00000100 /* Reads the floating point register in OP_*_FT. */ #define INSN_READ_FPR_T 0x00000200 +/* Reads the floating point register in OP_*_FR. */ +#define INSN_READ_FPR_R 0x00000400 /* Modifies coprocessor condition code. */ -#define INSN_WRITE_COND_CODE 0x00000400 +#define INSN_WRITE_COND_CODE 0x00000800 /* Reads coprocessor condition code. */ -#define INSN_READ_COND_CODE 0x00000800 +#define INSN_READ_COND_CODE 0x00001000 /* TLB operation. */ -#define INSN_TLB 0x00001000 -/* RFE (return from exception) instruction. */ -#define INSN_RFE 0x00002000 +#define INSN_TLB 0x00002000 /* Reads coprocessor register other than floating point register. */ #define INSN_COP 0x00004000 /* Instruction loads value from memory, requiring delay. */ @@ -232,6 +244,8 @@ struct mips_opcode #define INSN_4650 0x30000000 /* MIPS ISA 4 instruction (R8000). */ #define INSN_ISA4 0x40000000 +/* LSI R4010 instruction. */ +#define INSN_4010 0x50000000 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ -- 2.30.2