From b609fa1daa3dc6da4fbf91fcf3f818d6e1d00f2e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 14 Nov 2018 19:55:32 +0000 Subject: [PATCH] update branch / fp compare, clarify --- simple_v_extension/specification.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index e7e95e1f0..995c892a1 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -963,6 +963,13 @@ Where vectorisation is present on either or both src registers, the branch may stil go ahead if any only if *all* tests succeed (i.e. excluding those tests that are predicated out). +Note that when either src1 or src2 have zero-predication enabled, +a cleared bit in the respective predicate (src1's predicate register +or src2's predicate register, respectively) indicates that a zero is passed +into the compare unit (instead of the corresponding respective src1 or +src2 element), whilst a set bit indicates that the src1 (or src2) element +be passed into the compare unit. + Note that just as with the standard (scalar, non-predicated) branch operations, BLE, BGT, BLEU and BTGU may be synthesised by inverting src1 and src2. -- 2.30.2