From b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Nov 2019 12:46:19 +0000 Subject: [PATCH] Update CHANGELOG and README Signed-off-by: David Shah --- CHANGELOG | 2 ++ README.md | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 1fc139d49..a49c27b05 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -51,6 +51,8 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx - Added "check -mapped" + - Added checking of SystemVerilog always block types (always_comb, + always_latch and always_ff) Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/README.md b/README.md index db7810cb4..e46971526 100644 --- a/README.md +++ b/README.md @@ -371,6 +371,11 @@ Verilog Attributes and non-standard features for example, to specify the clk-to-Q delay of a flip-flop for consideration during techmapping. +- The frontend sets attributes ``always_comb``, ``always_latch`` and + ``always_ff`` on processes derived from SystemVerilog style always blocks + according to the type of the always. These are checked for correctness in + ``proc_dlatch``. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset -- 2.30.2