From b61315259dadad0551b1575e8b4ae0b034201513 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 2 May 2022 07:28:54 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 1d576b902..4c6020b64 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -40,10 +40,6 @@ Table of contents This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]]. -The plan is to create an encoding for SVP64, then to create an encoding -for SVP48, then to reorganize them both to improve field overlap, -reducing the amount of decoder hardware necessary. - All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB and counting up as you move to the LSB end). All bit ranges are inclusive (so `4:6` means bits 4, 5, and 6). @@ -57,6 +53,10 @@ suffix. The prefix always comes before the suffix in PC order. svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict. +Subset implementations in hardware are permitted, as long as certain +rules are followed, allowing for full soft-emulation including future +revisions. Details in the [[svp64/appendix]]. + ## SVP64 encoding features A number of features need to be compacted into a very small space of only 24 bits: @@ -74,28 +74,25 @@ This document focusses specifically on how that fits into available space. The For the new fields added in SVP64, instructions that have any of their fields set to a reserved value must cause an illegal instruction trap, -to allow emulation of future instruction sets. This includes SVP64 SPRs. +to allow emulation of future instruction sets, or for subsets of SVP64 +to be implemented in hardware and the rest emulated. +This includes SVP64 SPRs: reading or writing values which are not +supported in hardware must also raise illegal instruction traps +in order to allow emulation. Unless otherwise stated, reserved values are always all zeros. This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition is intended the red keyword `RESERVED` is used. -# Identity Behaviour +# Scalar Identity Behaviour SVP64 is designed so that when the prefix is all zeros, and VL=1, no effect or influence occurs (no augmentation) such that all standard OpenPOWER -v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation"). +v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation"). Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix) - whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation"). - -The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself. - -Implementors intending only to implement Scalar operations (identity behaviour only) -are however required to at least support the SVSTATE -SPR, which if nonzero (no longer identity behaviour) must cause all SVP64 instructions to raise an illegal instruction trap. This allows full -soft-implementation of SVP64. + whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation"). # Register Naming and size -- 2.30.2