From b62561e141cc169e8e67f3e360b907e119d0b328 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Dec 2021 09:53:25 +0000 Subject: [PATCH] include SPR.TB in SPR FU --- src/soc/fu/spr/main_stage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py index a73c6be9..64676e44 100644 --- a/src/soc/fu/spr/main_stage.py +++ b/src/soc/fu/spr/main_stage.py @@ -57,7 +57,7 @@ class SPRMainStage(PipeModBase): with m.Switch(spr): # fast SPRs first with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, - SPR.SRR1, SPR.XER, SPR.DEC): + SPR.SRR1, SPR.XER, SPR.DEC, SPR.TB): comb += fast1_o.data.eq(a_i) comb += fast1_o.ok.eq(1) # XER is constructed -- 2.30.2