From b640dfcd0506253231b93c03de7ee393fb0dfc46 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Mar 2017 05:45:00 +1000 Subject: [PATCH] radv: don't emit no color formats. (v3) If we had no rasterization, we'd emit SPI color format as all 0's the hw dislikes this, add the workaround from radeonsi. Found while debugging tessellation v2: handle at pipeline stage, we have to handle it after we process the fragment shader. (Bas) v3: simplify even further, remove old fallback. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_pipeline.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 094d636fc5c..45277b94fa1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -888,8 +888,6 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, if (blend_mrt0_is_dual_src) col_format |= (col_format & 0xf) << 4; - if (!col_format) - col_format |= V_028714_SPI_SHADER_32_R; blend->spi_shader_col_format = col_format; } @@ -1602,6 +1600,25 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable; /* prim vertex count will need TESS changes */ pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim]; + + /* Ensure that some export memory is always allocated, for two reasons: + * + * 1) Correctness: The hardware ignores the EXEC mask if no export + * memory is allocated, so KILL and alpha test do not work correctly + * without this. + * 2) Performance: Every shader needs at least a NULL export, even when + * it writes no color/depth output. The NULL export instruction + * stalls without this setting. + * + * Don't add this to CB_SHADER_MASK. + */ + if (!pipeline->graphics.blend.spi_shader_col_format) { + struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; + if (!ps->info.fs.writes_z && + !ps->info.fs.writes_stencil && + !ps->info.fs.writes_sample_mask) + pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; + } const VkPipelineVertexInputStateCreateInfo *vi_info = pCreateInfo->pVertexInputState; -- 2.30.2