From b659082e4a72209af62a19668800bb6334a437d7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:13:06 +0200 Subject: [PATCH] hierarchy - proc reorder --- tests/efinix/add_sub.ys | 1 + tests/efinix/adffs.ys | 8 ++++---- tests/efinix/dffs.ys | 4 ++-- tests/efinix/latches.ys | 6 +++--- tests/efinix/logic.ys | 1 + tests/efinix/mux.ys | 8 ++++---- 6 files changed, 15 insertions(+), 13 deletions(-) diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys index 67fa9f2e7..8bd28c68e 100644 --- a/tests/efinix/add_sub.ys +++ b/tests/efinix/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys index 3471a0a80..791626428 100644 --- a/tests/efinix/adffs.ys +++ b/tests/efinix/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -25,8 +25,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -38,8 +38,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys index fe8d93123..cdd288233 100644 --- a/tests/efinix/dffs.ys +++ b/tests/efinix/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-count 1 t:EFX_GBUFCE select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys index f729c3bd9..899d024ce 100644 --- a/tests/efinix/latches.ys +++ b/tests/efinix/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix cd latchn # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys index c2a7f5169..fdedb337b 100644 --- a/tests/efinix/logic.ys +++ b/tests/efinix/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys index efe27583d..71a9681de 100644 --- a/tests/efinix/mux.ys +++ b/tests/efinix/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -11,8 +11,8 @@ select -assert-count 1 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -21,8 +21,8 @@ select -assert-count 2 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -31,8 +31,8 @@ select -assert-count 5 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- 2.30.2