From b6a394bc50291ea97f8fb60f5538e37042dbb0b5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 May 2020 01:40:34 +0100 Subject: [PATCH] add extra INT regs port for now, add Fast Regfile --- src/soc/regfile/regfiles.py | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 15ddc7ca..6f819755 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -29,13 +29,41 @@ class IntRegs(RegFileArray): """IntRegs * QTY 32of 64-bit registers - * 3R1W + * 3R2W * Array-based unary-indexed (not binary-indexed) * write-through capability (read on same cycle as write) """ def __init__(self): super().__init__(64, 32) - self.w_ports = [self.write_port("dest")] + self.w_ports = [self.write_port("dest1", + self.write_port("dest2")] # for now (LD/ST update) + self.r_ports = [self.write_port("src1"), + self.write_port("src2"), + self.write_port("src3")] + + +# Fast SPRs Regfile +class FastRegs(RegFileArray): + """FastRegs + + FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2 + + * QTY 8of 64-bit registers + * 3R2W + * Array-based unary-indexed (not binary-indexed) + * write-through capability (read on same cycle as write) + """ + PC = 0 + MSR = 1 + CTR = 2 + LR = 3 + TAR = 4 + SRR1 = 5 + SRR2 = 6 + def __init__(self): + super().__init__(64, 8) + self.w_ports = [self.write_port("dest1", + self.write_port("dest2")] self.r_ports = [self.write_port("src1"), self.write_port("src2"), self.write_port("src3")] @@ -69,6 +97,9 @@ class XERRegs(VirtualRegPort): * Array-based unary-indexed (not binary-indexed) * write-through capability (read on same cycle as write) """ + SO=0 # this is actually 2-bit but we ignore 1 bit of it + CA=1 # CA and CA32 + OV=2 # OV and OV32 def __init__(self): super().__init__(6, 2) self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines) -- 2.30.2