From b6aee5d13d5919381c40e886b0a2a00a4e5d5c4f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 May 2020 15:06:02 +0100 Subject: [PATCH] comment where ALUIntermediateData to go --- src/soc/alu/main_stage.py | 2 +- src/soc/alu/output_stage.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index 07fb0180..7d79b1a1 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -18,7 +18,7 @@ class ALUMainStage(PipeModBase): return ALUInputData(self.pspec) def ospec(self): - return ALUOutputData(self.pspec) + return ALUOutputData(self.pspec) # TODO: ALUIntermediateData def elaborate(self, platform): m = Module() diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py index 1a8a82b6..188ea4ab 100644 --- a/src/soc/alu/output_stage.py +++ b/src/soc/alu/output_stage.py @@ -13,7 +13,7 @@ class ALUOutputStage(PipeModBase): super().__init__(pspec, "output") def ispec(self): - return ALUOutputData(self.pspec) + return ALUOutputData(self.pspec) # TODO: ALUIntermediateData def ospec(self): return ALUOutputData(self.pspec) -- 2.30.2