From b6b2b27809b9ce1cb8fdeb63fb4244c8a584434e Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 16 Oct 2018 14:58:18 -0500 Subject: [PATCH] blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP Cc: mesa-stable@lists.freedesktop.org Suggested-by: Francisco Jerez Reviewed-by: Kenneth Graunke --- src/intel/blorp/blorp_genX_exec.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 7a8c45dbee5..065980616ec 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -1642,6 +1642,15 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch, blorp_emit_cc_viewport(batch); } + /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the + * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch + * even when WM_HZ_OP is active. However, WM thread dispatch is normally + * disabled for HiZ ops and it appears that force-enabling it can lead to + * GPU hangs on at least Skylake. Since we don't know the current state of + * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP. + */ + blorp_emit(batch, GENX(3DSTATE_WM), wm); + /* If we can't alter the depth stencil config and multiple layers are * involved, the HiZ op will fail. This is because the op requires that a * new config is emitted for each additional layer. -- 2.30.2