From b6b3661a2e308bc611b50930165661b130d50706 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Tue, 24 Nov 2015 18:46:07 +0000 Subject: [PATCH] rs6000.md (UNSPEC_XSRDPI): New unspec. 2015-11-24 David Edelsohn Michael Meissner * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec. (Fv2): New mode attribute to be used when ISA 2.06 instructions are used on SF/DF values. (abs2_fpr): Use instead of . (nabs2_fpr): Likewise. (neg2_fpr): Likewise. (copysign3_fcpsgn): Likewise. (smax3_vsx): Likewise. (smin3_vsx): Likewise. (floatsi2_lfiwax): Likewise. (floatunssi2_lfiwz): Likewise. (fctiwz_): Likewise. (fctiwuz_): Likewise. (btrunc2): Likewise. (ceil2): Likewise. (floor2): Likewise. (xsrdpi): Add support for the lround function. (lround2): Likewise. Co-Authored-By: Michael Meissner From-SVN: r230829 --- gcc/ChangeLog | 22 ++++++++ gcc/config/rs6000/rs6000.md | 106 +++++++++++++++++++++++------------- 2 files changed, 90 insertions(+), 38 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a76a86602a1..2f990dbad8d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2015-11-24 David Edelsohn + Michael Meissner + + * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec. + (Fv2): New mode attribute to be used when ISA 2.06 instructions + are used on SF/DF values. + (abs2_fpr): Use instead of . + (nabs2_fpr): Likewise. + (neg2_fpr): Likewise. + (copysign3_fcpsgn): Likewise. + (smax3_vsx): Likewise. + (smin3_vsx): Likewise. + (floatsi2_lfiwax): Likewise. + (floatunssi2_lfiwz): Likewise. + (fctiwz_): Likewise. + (fctiwuz_): Likewise. + (btrunc2): Likewise. + (ceil2): Likewise. + (floor2): Likewise. + (xsrdpi): Add support for the lround function. + (lround2): Likewise. + 2015-11-24 Aditya Kumar Sebastian Pop diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8c1ddb02a9c..9d3a5b29c3f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -77,6 +77,7 @@ UNSPEC_FRIN UNSPEC_FRIP UNSPEC_FRIZ + UNSPEC_XSRDPI UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_RELD_MPIC ; re-load_macho_picbase UNSPEC_MPIC_CORRECT ; macho_correct_pic @@ -491,8 +492,16 @@ ; SF/DF constraint for arithmetic on traditional floating point registers (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")]) -; SF/DF constraint for arithmetic on VSX registers -(define_mode_attr Fv [(SF "wy") (DF "ws") (DI "wi")]) +; SF/DF constraint for arithmetic on VSX registers using instructions added in +; ISA 2.06 (power7). This includes instructions that normally target DF mode, +; but are used on SFmode, since internally SFmode values are kept in the DFmode +; format. +(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wi")]) + +; SF/DF constraint for arithmetic on VSX registers. This is intended to be +; used for DFmode instructions added in ISA 2.06 (power7) and SFmode +; instructions added in ISA 2.07 (power8) +(define_mode_attr Fv2 [(SF "wy") (DF "ws") (DI "wi")]) ; SF/DF constraint for arithmetic on altivec registers (define_mode_attr Fa [(SF "wu") (DF "wv")]) @@ -4344,9 +4353,9 @@ "") (define_insn "*add3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fadd %0,%1,%2 @@ -4362,9 +4371,9 @@ "") (define_insn "*sub3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fsub %0,%1,%2 @@ -4380,9 +4389,9 @@ "") (define_insn "*mul3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fmul %0,%1,%2 @@ -4398,9 +4407,9 @@ "") (define_insn "*div3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR && !TARGET_SIMPLE_FPU" "@ fdiv %0,%1,%2 @@ -4409,8 +4418,8 @@ (set_attr "fp_type" "fp_div_")]) (define_insn "sqrt2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET__FPR && !TARGET_SIMPLE_FPU && (TARGET_PPC_GPOPT || (mode == SFmode && TARGET_XILINX_FPU))" "@ @@ -4421,8 +4430,8 @@ ;; Floating point reciprocal approximation (define_insn "fre" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRES))] "TARGET_" "@ @@ -4431,8 +4440,8 @@ [(set_attr "type" "fp")]) (define_insn "*rsqrt2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_RSQRT))] "RS6000_RECIP_HAVE_RSQRTE_P (mode)" "@ @@ -4443,8 +4452,8 @@ ;; Floating point comparisons (define_insn "*cmp_fpr" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") - (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fcmpu %0,%1,%2 @@ -5500,6 +5509,27 @@ [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_")]) +(define_insn "*xsrdpi2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_XSRDPI))] + "TARGET__FPR && TARGET_VSX" + "xsrdpi %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) + +(define_expand "lrounddi2" + [(set (match_dup 2) + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")] + UNSPEC_XSRDPI)) + (set (match_operand:DI 0 "gpc_reg_operand" "=d") + (unspec:DI [(match_dup 2)] + UNSPEC_FCTID))] + "TARGET__FPR && TARGET_VSX" +{ + operands[2] = gen_reg_rtx (mode); +}) + ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" [(set (match_operand:SI 0 "memory_operand" "=Z") @@ -12468,11 +12498,11 @@ "") (define_insn "*fma4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "%,,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") - (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))] + (match_operand:SFDF 1 "gpc_reg_operand" "%,,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))] "TARGET__FPR" "@ fmadd %0,%1,%2,%3 @@ -12492,11 +12522,11 @@ "") (define_insn "*fms4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") - (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] "TARGET__FPR" "@ fmsub %0,%1,%2,%3 @@ -12539,12 +12569,12 @@ "") (define_insn "*nfma4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") - (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] "TARGET__FPR" "@ fnmadd %0,%1,%2,%3 @@ -12565,13 +12595,13 @@ "") (define_insn "*nfmssf4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") (neg:SFDF - (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))))] + (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))))] "TARGET__FPR" "@ fnmsub %0,%1,%2,%3 -- 2.30.2