From b6bc040142bd108e188424bfa9c415272571429b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 20 Mar 2017 14:28:40 +0100
Subject: [PATCH] boards/platforms/arty: add spi pins

---
 litex/boards/platforms/arty.py | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index d4c88eae..15283ece 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -37,6 +37,14 @@ _io = [
         Subsignal("rx", Pins("A9")),
         IOStandard("LVCMOS33")),
 
+    ("spi", 0,
+        Subsignal("clk", Pins("F1")),
+        Subsignal("cs_n", Pins("C1")),
+        Subsignal("mosi", Pins("H1")),
+        Subsignal("miso", Pins("G1")),
+        IOStandard("LVCMOS33")
+    ),
+
     ("spiflash_4x", 0,  # clock needs to be accessed through STARTUPE2
         Subsignal("cs_n", Pins("L13")),
         Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
@@ -51,6 +59,7 @@ _io = [
         IOStandard("LVCMOS33")
     ),
 
+
     ("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
 
     ("ddram", 0,
-- 
2.30.2