From b6cb34e7043813cedda232ee96cd3c5699fcf714 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Feb 2021 14:42:35 +0000 Subject: [PATCH] move SVP64PrefixDecoder to separate module --- src/soc/decoder/power_decoder2.py | 50 +-------------------- src/soc/decoder/power_svp64_prefix.py | 62 +++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 49 deletions(-) create mode 100644 src/soc/decoder/power_svp64_prefix.py diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index bfa1ab60..b0ecfa35 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -18,6 +18,7 @@ from nmutil.extend import exts from soc.experiment.mem_types import LDSTException +from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder from soc.decoder.power_regspec_map import regspec_decode_read from soc.decoder.power_regspec_map import regspec_decode_write from soc.decoder.power_decoder import create_pdecode @@ -1351,51 +1352,6 @@ class PowerDecode2(PowerDecodeSubset): comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state" -# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/ -# identifies if an instruction is a SVP64-encoded prefix, and extracts -# the 24-bit SVP64 context (RM) if it is -class SVP64PrefixDecoder(Elaboratable): - - def __init__(self): - self.opcode_in = Signal(32, reset_less=True) - self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True) - self.is_svp64_mode = Signal(1, reset_less=True) - self.svp64_rm = Signal(24, reset_less=True) - self.bigendian = Signal(reset_less=True) - - def elaborate(self, platform): - m = Module() - opcode_in = self.opcode_in - comb = m.d.comb - # sigh copied this from TopPowerDecoder - # raw opcode in assumed to be in LE order: byte-reverse it to get BE - raw_le = self.raw_opcode_in - l = [] - for i in range(0, 32, 8): - l.append(raw_le[i:i+8]) - l.reverse() - raw_be = Cat(*l) - comb += opcode_in.eq(Mux(self.bigendian, raw_be, raw_le)) - - # start identifying if the incoming opcode is SVP64 prefix) - major = sel(m, opcode_in, SVP64P.OPC) - ident = sel(m, opcode_in, SVP64P.SVP64_7_9) - - comb += self.is_svp64_mode.eq( - (major == Const(1, 6)) & # EXT01 - (ident == Const(0b11, 2)) # identifier bits - ) - - with m.If(self.is_svp64_mode): - # now grab the 24-bit ReMap context bits, - rm = sel(m, opcode_in, SVP64P.RM) - comb += self.svp64_rm.eq(rm) - - return m - - def ports(self): - return [self.opcode_in, self.raw_opcode_in, self.is_svp64_mode, - self.svp64_rm, self.bigendian] def get_rdflags(e, cu): rdl = [] @@ -1408,10 +1364,6 @@ def get_rdflags(e, cu): if __name__ == '__main__': - svp64 = SVP64PowerDecoder() - vl = rtlil.convert(svp64, ports=svp64.ports()) - with open("svp64_dec.il", "w") as f: - f.write(vl) pdecode = create_pdecode() dec2 = PowerDecode2(pdecode) vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports()) diff --git a/src/soc/decoder/power_svp64_prefix.py b/src/soc/decoder/power_svp64_prefix.py new file mode 100644 index 00000000..13352ebf --- /dev/null +++ b/src/soc/decoder/power_svp64_prefix.py @@ -0,0 +1,62 @@ +"""SVP64 Prefix Decoder + +""" + +from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat +from nmigen.cli import rtlil +from nmutil.util import sel + +from soc.consts import SVP64P + +# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/ +# identifies if an instruction is a SVP64-encoded prefix, and extracts +# the 24-bit SVP64 context (RM) if it is +class SVP64PrefixDecoder(Elaboratable): + + def __init__(self): + self.opcode_in = Signal(32, reset_less=True) + self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True) + self.is_svp64_mode = Signal(1, reset_less=True) + self.svp64_rm = Signal(24, reset_less=True) + self.bigendian = Signal(reset_less=True) + + def elaborate(self, platform): + m = Module() + opcode_in = self.opcode_in + comb = m.d.comb + # sigh copied this from TopPowerDecoder + # raw opcode in assumed to be in LE order: byte-reverse it to get BE + raw_le = self.raw_opcode_in + l = [] + for i in range(0, 32, 8): + l.append(raw_le[i:i+8]) + l.reverse() + raw_be = Cat(*l) + comb += opcode_in.eq(Mux(self.bigendian, raw_be, raw_le)) + + # start identifying if the incoming opcode is SVP64 prefix) + major = sel(m, opcode_in, SVP64P.OPC) + ident = sel(m, opcode_in, SVP64P.SVP64_7_9) + + comb += self.is_svp64_mode.eq( + (major == Const(1, 6)) & # EXT01 + (ident == Const(0b11, 2)) # identifier bits + ) + + with m.If(self.is_svp64_mode): + # now grab the 24-bit ReMap context bits, + rm = sel(m, opcode_in, SVP64P.RM) + comb += self.svp64_rm.eq(rm) + + return m + + def ports(self): + return [self.opcode_in, self.raw_opcode_in, self.is_svp64_mode, + self.svp64_rm, self.bigendian] + + +if __name__ == '__main__': + svp64 = SVP64PrefixDecoder() + vl = rtlil.convert(svp64, ports=svp64.ports()) + with open("svp64_prefix_dec.il", "w") as f: + f.write(vl) -- 2.30.2