From b6e66876cedb9474af9ec34953fea633d6e81046 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Apr 2019 04:09:00 +0100
Subject: [PATCH] add twin buf-unbuf pipe chain

---
 src/add/test_buf_pipe.py | 49 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 93732cb4..17caa176 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -677,6 +677,43 @@ class ExampleUnBufDelayedPipe(UnbufferedPipeline):
         m.submodules.stage = self.stage
         return m
 
+######################################################################
+# Test 999
+######################################################################
+
+class ExampleBufAdd1Pipe(BufferedPipeline):
+
+    def __init__(self):
+        stage = ExampleStageCls()
+        BufferedPipeline.__init__(self, stage)
+
+
+class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
+
+    def __init__(self):
+        stage = ExampleStageCls()
+        UnbufferedPipeline.__init__(self, stage)
+
+
+class ExampleBufUnBufPipe(ControlBase):
+    """ Example of how to do delayed pipeline, where the stage signals
+        whether it is ready.
+    """
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        #pipe1 = ExampleBufPipe()
+        pipe1 = ExampleBufAdd1Pipe()
+        pipe2 = ExampleUnBufAdd1Pipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
 
 ######################################################################
 # Unit Tests
@@ -806,3 +843,15 @@ if __name__ == '__main__':
     with open("test_unbufpipe13.il", "w") as f:
         f.write(vl)
 
+    print ("test 999")
+    dut = ExampleBufUnBufPipe()
+    data = data_chain1()
+    test = Test5(dut, test9_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufunbuf999.il", "w") as f:
+        f.write(vl)
+
-- 
2.30.2