From b6f21db2f45985aaeffa2a41daf5e4edf386b16c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 10:05:19 +0100 Subject: [PATCH] AddingPeripherals.mdwn --- docs/AddingPeripherals.mdwn | 22 +++++++++++++++++++++- src/bsv/peripheral_gen/base.py | 20 ++++++++++++++++---- src/bsv/peripheral_gen/sdram.py | 4 +++- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn index ae00d55..cbe2c30 100644 --- a/docs/AddingPeripherals.mdwn +++ b/docs/AddingPeripherals.mdwn @@ -424,7 +424,8 @@ now they are to be connected *automatically* (on the peripheral side) to the IO pads in the pinmux. However, at the time of writing this is not fully understood by the author, so the fastifdecl and extfastifinstance functions are modified to generate the correct output but the code is -*commented out*: +*commented out*, and the corresponding manual declarations of sdram_out +removed. def extfastifinstance(self, name, count): return "// TODO" + self._extifinstance(name, count, "_out", "", True, @@ -434,4 +435,23 @@ functions are modified to generate the correct output but the code is return "// (*always_ready*) interface " + \ "Ifc_sdram_out sdr{0}_out;".format(count) +Next, again searching for signs of the "hand-written" code, we encounter +the fabric connectivity, which wires the SDRAM to the AXI4. We note however +that there is not just one AXI slave device but *two*: one for the SDRAM +itself and one for *configuring* the SDRAM. We therefore need to be +quite careful about assigning these, as will be subsequently explained. +First however, the two AXI4 slave interfaces of this peripheral are +declared: + class sdram(PBase): + + ... + ... + def _mk_connection(self, name=None, count=0): + return ["sdr{0}.axi4_slave_sdram", + "sdr{0}.axi4_slave_cntrl_reg"] + +Note that, again, in case multiple instances are ever to be added, the +python "format" string "{0}" is inserted so that it can be substituted +with the numerical identifier suffix. Also note that the order +of declaration of these two AXI4 slave is **important**. diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 4758655..33057cf 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -349,16 +349,28 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( name = self.name print "PBase mk_master_conn", self.name, count aname = self.axi_master_name(name, count, typ) - con = self._mk_connection(name, count, True).format(count, aname) - return self.__mk_master_connection(con, aname, fabricname) + ret = [] + connections = self._mk_connection(name, count, True) + if not isinstance(connections, list): + connections = [connections] + for con in connections: + con = con.format(count, aname) + ret.append(self.__mk_master_connection(con, aname, fabricname)) + return '\n'.join(ret) def mk_connection(self, count, fabricname, typ, name=None): if name is None: name = self.name print "PBase mk_conn", self.name, count aname = self.axi_slave_name(name, count, typ) - con = self._mk_connection(name, count).format(count, aname) - return self.__mk_connection(con, aname, fabricname) + ret = [] + connections = self._mk_connection(name, count) + if not isinstance(connections, list): + connections = [connections] + for con in connections: + con = con.format(count, aname) + ret.append(self.__mk_connection(con, aname, fabricname)) + return '\n'.join(ret) def _mk_connection(self, name=None, count=0): return '' diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py index 9cdf1fd..76d5481 100644 --- a/src/bsv/peripheral_gen/sdram.py +++ b/src/bsv/peripheral_gen/sdram.py @@ -24,7 +24,9 @@ class sdram(PBase): return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);" def _mk_connection(self, name=None, count=0): - return "sdr{0}.axi_side" + return ["sdr{0}.axi4_slave_sdram", + "sdr{0}.axi4_slave_cntrl_reg"] + def pinname_in(self, pname): return {'ta': 'sdram_side.m_tAn', -- 2.30.2