From b7003d089e1147469a807256dc4721283fce3a37 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 13:37:52 +0000 Subject: [PATCH] ULX3S is an LFE5U-85F ECP5 not a LFE5UMG-85F --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 22bd160..192648c 100644 --- a/Makefile +++ b/Makefile @@ -160,12 +160,12 @@ FPGA_TARGET ?= ORANGE-CRAB ifeq ($(FPGA_TARGET), ULX3S) RESET_LOW=true CLK_INPUT=25000000 -CLK_FREQUENCY=25000000 +CLK_FREQUENCY=12500000 LPF=constraints/ulx3s.lpf PACKAGE=CABGA381 -NEXTPNR_FLAGS=--um5g-85k --freq 25 +NEXTPNR_FLAGS=--85k --freq 25 OPENOCD_JTAG_CONFIG=openocd/ulx3s.cfg -OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg +OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg endif # OrangeCrab with ECP85 @@ -230,7 +230,7 @@ GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE -gEXTERNAL_CORE=$(EXTERNAL_CORE) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" -- 2.30.2