From b7270a4037973e31f0414eace338e62e7ee984be Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 22 Dec 2020 14:05:47 +0000
Subject: [PATCH]

---
 openpower/sv/vector_ops.mdwn | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 openpower/sv/vector_ops.mdwn

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
new file mode 100644
index 000000000..43e6ab338
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+++ b/openpower/sv/vector_ops.mdwn
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+# SV Vector Operations.
+
+The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVC512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
+
+Links:
+
+* <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions>
-- 
2.30.2