From b72ff402742d959e4f77581e54fd7de3e09a06f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 13 Aug 2020 13:59:48 +0100 Subject: [PATCH] plenty of time to wait for operand, so use "sync" in MultiCompUnit --- src/soc/experiment/compalu_multi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 514dc3fa..428e1b09 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -285,8 +285,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # a regfile port because this particular output is not valid" m.d.comb += self.wrmask.eq(Cat(*wrok)) - # pass the operation to the ALU - m.d.comb += self.get_op().eq(oper_r) + # pass operation to the ALU (sync because time to wait for src reads) + m.d.sync += self.get_op().eq(oper_r) # create list of src/alu-src/src-latch. override 1st and 2nd one below. # in the case, for ALU and Logical pipelines, we assume RB is the -- 2.30.2