From b73d52c1ef93d0883d582f8e6f9f560f4e0566b1 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Mon, 24 Oct 2022 21:12:04 +0300 Subject: [PATCH] minor_4.csv: support shadd/shadduw instructions --- openpower/isatables/minor_22.csv | 3 +++ src/openpower/decoder/power_enums.py | 1 + 2 files changed, 4 insertions(+) diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index 0935512a..e696ad4a 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -31,10 +31,13 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0101001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +--01101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +--11101110-,ALU,OP_SHADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,shadduw,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1001110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdacu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg + # Vector bitmanip 0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 71777760..9c6ec88b 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -710,6 +710,7 @@ class MicrOp(Enum): OP_DIVMOD2DU = 100 OP_DSHL = 101 OP_DSHR = 102 + OP_SHADD = 103 @unique -- 2.30.2