From b766af0d992a9d4c478f40b652d7515609b9f871 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Sep 2013 15:07:23 +0200 Subject: [PATCH] uart2csr: add pads parameter --- examples/de0_nano/top.py | 5 +---- miscope/com/uart2csr/__init__.py | 9 +++------ 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 0582762a..617399ef 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -58,10 +58,7 @@ class SoC(Module): self.submodules.mila = MiLa(mila_width, mila_depth, [term], rle=True) # Uart2Csr - self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200) - uart_pads = platform.request("serial") - self.comb += uart_pads.tx.eq(self.uart2csr.tx) - self.comb += self.uart2csr.rx.eq(uart_pads.rx) + self.submodules.uart2csr = uart2csr.Uart2Csr(platform.request("serial"), clk_freq, 115200) # Csr Interconnect self.submodules.csrbankarray = csrgen.BankArray(self, diff --git a/miscope/com/uart2csr/__init__.py b/miscope/com/uart2csr/__init__.py index e8e569ce..3f97ad3e 100644 --- a/miscope/com/uart2csr/__init__.py +++ b/miscope/com/uart2csr/__init__.py @@ -10,10 +10,7 @@ READ_CMD = 0x02 CLOSE_CMD = 0x03 class Uart2Csr(Module): - def __init__(self, clk_freq, baud): - # Uart interface - self.rx = Signal() - self.tx = Signal() + def __init__(self, pads, clk_freq, baud): # Csr interface self.csr = csr.Interface() @@ -27,8 +24,8 @@ class Uart2Csr(Module): # In/Out # self.comb +=[ - uart.rx.eq(self.rx), - self.tx.eq(uart.tx) + uart.rx.eq(pads.rx), + pads.tx.eq(uart.tx) ] cmd = Signal(8) -- 2.30.2