From b76ab666387570fd51d820a35660de07b207ba0e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 29 Jan 2021 22:39:44 +0000 Subject: [PATCH] adjust SVP64RM class to output more PowerDecoder-friendly csv augmentation add SVEXTRA power_enum extend PowerDecoder fields (sv in/out regs) --- src/soc/decoder/power_decoder.py | 15 ++++++++++++++- src/soc/decoder/power_enums.py | 9 +++++++++ src/soc/decoder/power_svp64.py | 18 ++++++++++++------ 3 files changed, 35 insertions(+), 7 deletions(-) diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index 2b01d4d4..6712cd1d 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -92,7 +92,7 @@ from nmigen import Module, Elaboratable, Signal, Cat, Mux from nmigen.cli import rtlil from soc.decoder.power_enums import (Function, Form, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, - SVEtype, SVPtype, # Simple-V + SVEXTRA, SVEtype, SVPtype, # Simple-V RC, LdstLen, LDSTMode, CryIn, single_bit_flags, CRInSel, CROutSel, get_signal_name, @@ -127,6 +127,12 @@ power_op_types = {'function_unit': Function, 'out_sel': OutSel, 'cr_in': CRInSel, 'cr_out': CROutSel, + 'sv_in1': SVEXTRA, + 'sv_in2': SVEXTRA, + 'sv_in3': SVEXTRA, + 'sv_out': SVEXTRA, + 'sv_cr_in': SVEXTRA, + 'sv_cr_out': SVEXTRA, 'ldst_len': LdstLen, 'upd': LDSTMode, 'rc_sel': RC, @@ -140,6 +146,12 @@ power_op_csvmap = {'function_unit': 'unit', 'in2_sel': 'in2', 'in3_sel': 'in3', 'out_sel': 'out', + 'sv_in1': 'sv_in1', + 'sv_in2': 'sv_in2', + 'sv_in3': 'sv_in3', + 'sv_out': 'sv_out', + 'sv_cr_in': 'sv_cr_in', + 'sv_cr_out': 'sv_cr_out', 'cr_in': 'CR in', 'cr_out': 'CR out', 'ldst_len': 'ldst len', @@ -209,6 +221,7 @@ class PowerOp: if field not in power_op_csvmap: continue csvname = power_op_csvmap[field] + print (field, ptype, csvname, row) val = row[csvname] if csvname == 'upd' and isinstance(val, int): # LDSTMode different val = ptype(val) diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py index 74c149e3..46e97d69 100644 --- a/src/soc/decoder/power_enums.py +++ b/src/soc/decoder/power_enums.py @@ -118,6 +118,15 @@ class SVEtype(Enum): EXTRA2 = 1 EXTRA3 = 2 +@unique +class SVEXTRA(Enum): + NONE = 0 + Idx0 = 1 + Idx1 = 2 + Idx2 = 3 + Idx3 = 4 + Idx_1_2 = 5 # due to weird BA/BB for crops + # supported instructions: make sure to keep up-to-date with CSV files # just like everything else _insns = [ diff --git a/src/soc/decoder/power_svp64.py b/src/soc/decoder/power_svp64.py index 85fc3974..d2efd16f 100644 --- a/src/soc/decoder/power_svp64.py +++ b/src/soc/decoder/power_svp64.py @@ -79,7 +79,10 @@ class SVP64RM: # dummy (blank) fields, first entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0', 'EXTRA3': '0', - 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE'}) + 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE', + 'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'}) + for fname in ['in1', 'in2', 'in3', 'out']: + entry['sv_%s' % fname] = 'NONE' # is this SVP64-augmented? asmcode = entry['comment'] @@ -111,22 +114,25 @@ class SVP64RM: if (fname != 'out' and regfield in svp64_src): extra_index = svp64_src[regfield] # ta-daa, we know in1/2/3/out's bit-offset - entry['sv_%s' % fname] = extra_index + if extra_index is not None: + entry['sv_%s' % fname] = "Idx"+str(extra_index) # TODO: CRs a little tricky, the power_enums.CRInSel is a bit odd. # ignore WHOLE_REG for now cr_in = entry['CR in'] - extra_index = None + extra_index = 'NONE' if cr_in in svp64_src: - entry['sv_cr_in'] = svp64_src[cr_in] + entry['sv_cr_in'] = "Idx"+str(svp64_src[cr_in]) elif cr_in == 'BA_BB': index1 = svp64_src.get('BA', None) index2 = svp64_src.get('BB', None) - entry['sv_cr_in'] = (index1, index2) + entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2) # CRout a lot easier. ignore WHOLE_REG for now cr_out = entry['CR out'] - entry['sv_cr_out'] = svp64_dest.get(cr_out, None) + extra_index = svp64_dest.get(cr_out, None) + if extra_index is not None: + entry['sv_cr_out'] = 'Idx%d' % extra_index # more enum-friendly Ptype names. should have done this in # sv_analysis.py, oh well -- 2.30.2