From b77859ebdabad209e46f8017eb7e833649171c99 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 10 May 2022 10:19:31 +0100 Subject: [PATCH] --- conferences/ics2022.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/conferences/ics2022.mdwn b/conferences/ics2022.mdwn index 9793a3409..a84684bb3 100644 --- a/conferences/ics2022.mdwn +++ b/conferences/ics2022.mdwn @@ -25,9 +25,11 @@ and conditional Graph walking, making full use of OpenCAPI's potential. Snitch also led the way, bringing back Auto-increment Load/Store from the CISC era, but hidden behind Tagged Registers connected to Coherent FIFOs leading indirectly to main Memory. Where both Snitch -and Extra-V used limited variants of Deterministic Loops as proof-of-concept -of the overall , ZOLC is -a much more extensive and well-defined +and Extra-V used limited variants of Deterministic Loops as +proof-of-concept to support their overall research, with only rudimentary +processing capability, +ZOLC is a much more deeply extensive and well-defined Deterministic Loop +Control system that can fit directly on top of a standard ISA. SVP64 takes the Zero-Overhead Loop concept firmly into Supercomputing Vector Processing territory, currently limited to the register file. -- 2.30.2