From b779d05d711dedb32f6aca85ba4f9b28be78e7ea Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Mon, 13 Apr 2020 18:35:57 +0200 Subject: [PATCH] radv: Add inputs read by TES to radv_shader_info. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Reviewed-by: Rhys Perry Part-of: --- src/amd/vulkan/radv_pipeline.c | 7 +++++++ src/amd/vulkan/radv_shader.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 984a095aad8..2e535a33e39 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2602,6 +2602,13 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, filled_stages |= (1 << MESA_SHADER_FRAGMENT); } + if (nir[MESA_SHADER_TESS_CTRL]) { + infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read = + nir[MESA_SHADER_TESS_EVAL]->info.inputs_read; + infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read = + nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read; + } + if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && nir[MESA_SHADER_TESS_CTRL]) { struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]}; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 23ff7ddcdcc..165df3afe2e 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -316,6 +316,8 @@ struct radv_shader_info { struct { uint64_t outputs_written; uint64_t patch_outputs_written; + uint64_t tes_inputs_read; + uint64_t tes_patch_inputs_read; unsigned tcs_vertices_out; uint32_t num_patches; uint32_t lds_size; -- 2.30.2