From b788cccfe2ff2b6897b73bbfe7e90e84899adec0 Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason@jlekstrand.net>
Date: Mon, 6 Jan 2020 22:14:29 -0600
Subject: [PATCH] intel/disasm: Fix decoding of src0 of SENDS

There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
---
 src/intel/compiler/brw_disasm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 7d821dbc1fa..31d932b9cba 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1446,7 +1446,7 @@ src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
          return src_sends_da(file,
                              devinfo,
                              BRW_REGISTER_TYPE_UD,
-                             brw_inst_send_src0_reg_file(devinfo, inst),
+                             BRW_GENERAL_REGISTER_FILE,
                              brw_inst_src0_da_reg_nr(devinfo, inst),
                              brw_inst_src0_da16_subreg_nr(devinfo, inst));
       } else {
-- 
2.30.2