From b78bd51050e432bde2cfedf6a5f778de4459f91e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 24 Feb 2020 18:26:30 +0000 Subject: [PATCH] make example as close to adder benchmark as possible --- experiments4/Makefile | 4 ++-- experiments4/add.py | 6 +++--- experiments4/coriolis2/ioring.py | 19 +++++++++---------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/experiments4/Makefile b/experiments4/Makefile index 8addfb5..d059192 100755 --- a/experiments4/Makefile +++ b/experiments4/Makefile @@ -7,8 +7,8 @@ YOSYS_FLATTEN = Yes CHIP = chip CORE = add - MARGIN = 5 - BOOMOPT = -A + MARGIN = 2 + BOOMOPT = # -A BOOGOPT = LOONOPT = NSL2VHOPT = -vasy # -split -p diff --git a/experiments4/add.py b/experiments4/add.py index 83e7a72..68aecc1 100644 --- a/experiments4/add.py +++ b/experiments4/add.py @@ -6,11 +6,11 @@ class ADD(Elaboratable): def __init__(self, width): self.a = Signal(width) self.b = Signal(width) - self.o = Signal(width) + self.f = Signal(width) def elaborate(self, platform): m = Module() - m.d.comb += self.eq(self.a + self.b) + m.d.sync += self.f.eq(self.a + self.b) return m @@ -21,4 +21,4 @@ def create_ilang(dut, ports, test_name): if __name__ == "__main__": alu = ADD(width=4) - create_ilang(alu, [alu.a, alu.b, alu.o], "add") + create_ilang(alu, [alu.a, alu.b, alu.f], "add") diff --git a/experiments4/coriolis2/ioring.py b/experiments4/coriolis2/ioring.py index 0951b57..cc8a055 100644 --- a/experiments4/coriolis2/ioring.py +++ b/experiments4/coriolis2/ioring.py @@ -4,24 +4,23 @@ from helpers import l, u, n def pad_nums(s, sep="_"): res = [] - for i in range(16): + for i in range(4): res.append("%s%s%d" % (s, sep, i)) return res a_pads = pad_nums("a") -o_pads = pad_nums("o") +o_pads = pad_nums("f") chip = { 'pads.ioPadGauge' : 'pxlib' - , 'pads.south' : a_pads[:8] + ["p_vddick_0", "p_vssick_0" ] + \ - a_pads[8:] + , 'pads.south' : a_pads[:2] + ["p_vddick_0", "p_vssick_0" ] + \ + a_pads[2:] , 'pads.east' : pad_nums("b") - , 'pads.north' : o_pads[:8] + ["p_vddeck_0", "p_vsseck_0" ] + \ - o_pads[8:] - , 'pads.west' : [ "op", - "p_clk_0", + , 'pads.north' : o_pads[:2] + ["p_vddeck_0", "p_vsseck_0" ] + \ + o_pads[2:] + , 'pads.west' : [ "p_clk_0", "rst", ] - , 'core.size' : ( l(3000), l(3000) ) - , 'chip.size' : ( l(5000), l(5000) ) + , 'core.size' : ( l(1000), l(1000) ) + , 'chip.size' : ( l(2500), l(2500) ) , 'chip.clockTree' : True } -- 2.30.2