From b7b9a1f0fb6086a2141042896e4713159c7c0362 Mon Sep 17 00:00:00 2001 From: sadullah Date: Mon, 27 Apr 2020 23:03:36 -0400 Subject: [PATCH] Linux works, LiteDRAM works (need cleaning, temporary push) --- litex/boards/targets/genesys2.py | 3 +- .../bp_fpga/ExampleBlackParrotSystem.v | 4 +- litex/soc/cores/cpu/blackparrot/core.py | 68 +++++++++---------- .../cpu/blackparrot/flist_litex.verilator | 5 +- .../cores/cpu/blackparrot/setEnvironment.sh | 3 +- litex/soc/software/bios/Makefile | 2 +- litex/soc/software/bios/boot.c | 13 +++- litex/soc/software/bios/sdram.c | 2 +- litex/soc/software/include/base/ctype.h | 6 +- litex/soc/software/libbase/libc.c | 7 +- litex/soc/software/libnet/tftp.c | 10 ++- litex/tools/litex_sim.py | 3 +- 12 files changed, 78 insertions(+), 48 deletions(-) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index d97b68a3..6b9c2c9c 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -46,10 +46,11 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + sys_clk_freq = int(50e6) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - + self.add_constant("UART_POLLING",None) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v index cdd1a95e..9eb86cb5 100644 --- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v +++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v @@ -171,7 +171,7 @@ bp_chip ); - bind bp_be_top +/* bind bp_be_top bp_be_nonsynth_tracer #(.cfg_p(cfg_p)) tracer @@ -207,7 +207,7 @@ bp_chip ,.priv_mode_i(be_mem.csr.priv_mode_n) ,.mpp_i(be_mem.csr.mstatus_n.mpp) ); - +*/ /*bind bp_be_top bp_be_nonsynth_perf #(.cfg_p(cfg_p)) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index e9ad4164..ccce090c 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -40,9 +40,9 @@ from litex.soc.cores.cpu import CPU CPU_VARIANTS = { "standard": "freechips.rocketchip.system.LitexConfig", } - +# -mcmodel=medany GCC_FLAGS = { - "standard": "-march=rv64ia -mabi=lp64 -O0 ", + "standard": "-march=rv64ia -mabi=lp64 -O0 ", } class BlackParrotRV64(CPU): @@ -52,15 +52,15 @@ class BlackParrotRV64(CPU): gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf64-littleriscv" - io_regions = {0x30000000: 0x20000000} # origin, length - + io_regions = {0x50000000: 0x10000000} # origin, length + @property def mem_map(self): return { - "ethmac" : 0x30000000, - "csr" : 0x40000000, - "rom" : 0x50000000, - "sram" : 0x51000000, + "csr" : 0x50000000, +# "ethmac" : 0x55000000, + "rom" : 0x70000000, + "sram" : 0x71000000, "main_ram" : 0x80000000, } @@ -81,33 +81,33 @@ class BlackParrotRV64(CPU): self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37) self.periph_buses = [idbus] self.memory_buses = [] - - # # # + self.buses = [wbn] self.cpu_params = dict( # clock, reset - i_clk_i = ClockSignal(), - i_reset_i = ResetSignal() | self.reset, - - # irq - i_interrupts = self.interrupt, - - # wishbone - i_wbm_dat_i = idbus.dat_r, - o_wbm_dat_o = idbus.dat_w, - i_wbm_ack_i = idbus.ack, - i_wbm_err_i = 0, - i_wbm_rty_i = 0, - o_wbm_adr_o = idbus.adr, - o_wbm_stb_o = idbus.stb, - o_wbm_cyc_o = idbus.cyc, - o_wbm_sel_o = idbus.sel, - o_wbm_we_o = idbus.we, - o_wbm_cti_o = idbus.cti, - o_wbm_bte_o = idbus.bte, - ) - - # add verilog sources + i_clk_i = ClockSignal(), + i_reset_i = ResetSignal() | self.reset, + + # irq + #i_interrupts = self.interrupt, + + #wishbone + i_wbm_dat_i = wbn.dat_r, + o_wbm_dat_o = wbn.dat_w, + i_wbm_ack_i = wbn.ack, + i_wbm_err_i = wbn.err, + #i_wbm_rty_i = 0, + o_wbm_adr_o = wbn.adr, + o_wbm_stb_o = wbn.stb, + o_wbm_cyc_o = wbn.cyc, + o_wbm_sel_o = wbn.sel, + o_wbm_we_o = wbn.we, + o_wbm_cti_o = wbn.cti, + o_wbm_bte_o = wbn.bte, + + ) + + # add verilog sources self.add_sources(platform, variant) def set_reset_address(self, reset_address): @@ -131,7 +131,7 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1] + line[s2:-1] - print("INCDIR" + vdir) + #print("INCDIR" + vdir) platform.add_verilog_include_path(vdir) #this line might be changed elif (temp[0]=='$') : s2 = line.find('/') @@ -139,7 +139,7 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1]+ line[s2:-1] - print(vdir) + #print(vdir) platform.add_source(vdir) #this line might be changed elif (temp[0] == '/'): assert("No support for absolute path for now") diff --git a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator index 65e8e1c4..ba656dc1 100644 --- a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator +++ b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator @@ -203,7 +203,7 @@ $BP_COMMON_DIR/src/v/bp_addr_map.v // bsg_ip_cores files $BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v // be files -$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v +//$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v // $BP_BE_DIR/test/common/bp_be_nonsynth_perf.v // me files // $BP_ME_DIR/test/common/bp_mem.v @@ -218,9 +218,10 @@ $BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v // top files $BP_TOP_DIR/test/common/bp_nonsynth_host.v // $BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v -$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v +//$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v // /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/wrapper.v // /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/test_bp.cpp +$BP_TOP_DIR/test/common/bp_monitor.cpp $BP_FPGA_DIR/bp2wb_convertor.v $BP_FPGA_DIR/ExampleBlackParrotSystem.v $BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh index d818ec52..079bb17f 100755 --- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh +++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh @@ -38,7 +38,8 @@ export SYSTEMC_INCLUDE=$BP_EXTERNAL_DIR/include export SYSTEMC_LIBDIR=$BP_EXTERNAL_DIR/lib-linux64 ## Add external tools and libraries to environment -export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH +export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR +#:$LD_LIBRARY_PATH #export PATH=$(BP_EXTERNAL_DIR)/bin:$(PATH) #export SYN_PATH=$(BP_TOP_DIR)/syn #export TB_PATH=$(BP_TOP_DIR)/test/tb diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile index cc3b973a..98dc44d5 100755 --- a/litex/soc/software/bios/Makefile +++ b/litex/soc/software/bios/Makefile @@ -2,7 +2,7 @@ include ../include/generated/variables.mak include $(SOC_DIRECTORY)/software/common.mak ifeq ($(CPU),blackparrot) -BP_LIBS = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0 +BP_LIBS = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/9.2.0/ BP_FLAGS = -lgcc endif # Permit TFTP_SERVER_PORT override from shell environment / command line diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c index 08b3be4a..274cd789 100644 --- a/litex/soc/software/bios/boot.c +++ b/litex/soc/software/bios/boot.c @@ -32,6 +32,8 @@ #include "sfl.h" #include "boot.h" +#define MEMTEST_DATA_SIZE2 (589824*4) + extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) @@ -59,7 +61,16 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u mtspr(SPR_EVBAR, addr); addr += 0x100; #endif - + + +/* volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE; + int i; + unsigned int rdata; + for(i=0;i='0') && (c<='9')) return 1; + return 0; +} #define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) #define islower(c) ((__ismask(c)&(_L)) != 0) #define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) diff --git a/litex/soc/software/libbase/libc.c b/litex/soc/software/libbase/libc.c index be48cf65..698ec59c 100644 --- a/litex/soc/software/libbase/libc.c +++ b/litex/soc/software/libbase/libc.c @@ -23,7 +23,7 @@ #include #include #include - +#include /** * strchr - Find the first occurrence of a character in a string * @s: The string to be searched @@ -375,7 +375,7 @@ void *memchr(const void *s, int c, size_t n) * @base: The number base to use */ unsigned long strtoul(const char *nptr, char **endptr, int base) -{ +{ printf("HI\n"); unsigned long result = 0,value; if (!base) { @@ -392,11 +392,14 @@ unsigned long strtoul(const char *nptr, char **endptr, int base) if (nptr[0] == '0' && toupper(nptr[1]) == 'X') nptr += 2; } + printf("HI2\n"); while (isxdigit(*nptr) && (value = isdigit(*nptr) ? *nptr-'0' : toupper(*nptr)-'A'+10) < base) { result = result*base + value; nptr++; + printf("HI4\n"); } + printf("HI3\n"); if (endptr) *endptr = (char *)nptr; return result; diff --git a/litex/soc/software/libnet/tftp.c b/litex/soc/software/libnet/tftp.c index 439b3e07..d5110738 100644 --- a/litex/soc/software/libnet/tftp.c +++ b/litex/soc/software/libnet/tftp.c @@ -117,10 +117,11 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, int i; int length_before; int spin = 0; + printf("DEBUGWTH?\n"); if(!microudp_arp_resolve(ip)) return -1; - + printf("DEBUG0\n"); microudp_set_callback(rx_callback); dst_buffer = buffer; @@ -129,6 +130,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, transfer_finished = 0; tries = 5; while(1) { + + printf("DEBUG1\n"); packet_data = microudp_get_tx_buffer(); len = format_request(packet_data, TFTP_RRQ, filename); microudp_send(PORT_IN, server_port, len); @@ -136,6 +139,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, microudp_service(); if((total_length > 0) || transfer_finished) break; } + + printf("DEBUG2\n"); if((total_length > 0) || transfer_finished) break; tries--; if(tries == 0) { @@ -144,6 +149,7 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, } } + printf("DEBUG3\n"); i = 12000000; length_before = total_length; while(!transfer_finished) { @@ -162,8 +168,10 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, microudp_service(); } + printf("DEBUG4\n"); microudp_set_callback(NULL); + printf("DEBUG5\n"); return total_length; } diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 987681d3..ebba204b 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -177,6 +177,7 @@ class SimSoC(SoCSDRAM): ident = "LiteX Simulation", ident_version=True, l2_reverse = False, **kwargs) + self.add_constant("UART_POLLING",None) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) @@ -353,7 +354,7 @@ def main(): sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness), **soc_kwargs) if args.ram_init is not None: - soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) + soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000) if args.with_ethernet: for i in range(4): soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i])) -- 2.30.2