From b7ec698d4063f0e0ae021050782004c523302b0c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 7 May 2019 19:58:04 +0200 Subject: [PATCH] Add test case from #997 Signed-off-by: Clifford Wolf --- tests/simple/dff_init.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v index be947042e..375ea5c4d 100644 --- a/tests/simple/dff_init.v +++ b/tests/simple/dff_init.v @@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk); n1 <= n1_inv; assign n1_inv = ~n1; endmodule + +module dff_test_997 (y, clk, wire4); +// https://github.com/YosysHQ/yosys/issues/997 + output wire [1:0] y; + input clk; + input signed wire4; + reg [1:0] reg10 = 0; + always @(posedge clk) begin + reg10 <= wire4; + end + assign y = reg10; +endmodule -- 2.30.2