From b7fa346690e88594c8fecccfe8be0f27e0b1265c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 19 Jul 2020 20:44:18 +0100 Subject: [PATCH 1/1] add issuer verilog generator --- src/soc/simple/issuer_verilog.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 src/soc/simple/issuer_verilog.py diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py new file mode 100644 index 00000000..17cbc4d7 --- /dev/null +++ b/src/soc/simple/issuer_verilog.py @@ -0,0 +1,26 @@ +"""simple core issuer verilog generator +""" + +import sys +from nmigen.cli import verilog + +from soc.config.test.test_loadstore import TestMemPspec +from soc.simple.issuer import TestIssuer + + +if __name__ == '__main__': + units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1, + 'spr': 1, + 'mul': 1, + 'shiftrot': 1} + pspec = TestMemPspec(ldst_ifacetype='bare_wb', + imem_ifacetype='bare_wb', + addr_wid=48, + mask_wid=8, + reg_wid=64, + units=units) + dut = TestIssuer(pspec) + + vl = verilog.convert(dut, ports=dut.ports(), name="test_issuer") + with open(sys.argv[1], "w") as f: + f.write(vl) -- 2.30.2