From b7fb80ccf514fe804cf112d7e8d11764ef93bca5 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 22 Jun 2016 22:51:12 -0700 Subject: [PATCH] Fix paddr_bits computation prior to VM setup --- riscv/processor.cc | 13 ++++--------- riscv/processor.h | 1 + 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index f030dfa..e2f44b5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -283,14 +283,10 @@ static bool validate_vm(int max_xlen, reg_t vm) return vm == VM_MBARE; } -static int paddr_bits(reg_t vm) +int processor_t::paddr_bits() { - switch (vm) { - case VM_SV32: return 34; - case VM_SV39: return 50; - case VM_SV48: return 50; - default: abort(); - } + assert(xlen == max_xlen); + return max_xlen == 64 ? 50 : 34; } void processor_t::set_csr(int which, reg_t val) @@ -379,8 +375,7 @@ void processor_t::set_csr(int which, reg_t val) (state.mie & ~state.mideleg) | (val & state.mideleg)); case CSR_SPTBR: { // upper bits of sptbr are the ASID; we only support ASID = 0 - reg_t vm = get_field(state.mstatus, MSTATUS_VM); - state.sptbr = val & (((reg_t)1 << (paddr_bits(vm) - PGSHIFT)) - 1); + state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1); break; } case CSR_SEPC: state.sepc = val; break; diff --git a/riscv/processor.h b/riscv/processor.h index 730ae78..2906bda 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -158,6 +158,7 @@ private: void take_interrupt(); // take a trap if any interrupts are pending void take_trap(trap_t& t, reg_t epc); // take an exception void disasm(insn_t insn); // disassemble and print an instruction + int paddr_bits(); void enter_debug_mode(uint8_t cause); -- 2.30.2