From b81880f1edfa5fc9a2c8aeec82efd527dfb5bd84 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 15:29:57 +0100 Subject: [PATCH] --- openpower/sv/rfc/001.mdwn | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/001.mdwn b/openpower/sv/rfc/001.mdwn index 246f14e06..dfb52509d 100644 --- a/openpower/sv/rfc/001.mdwn +++ b/openpower/sv/rfc/001.mdwn @@ -5,6 +5,7 @@ Links * +* * * * @@ -42,6 +43,27 @@ AMD and many other ISAs have been adding over the past 12 years. *Thus it becomes necesary to consider the Architectural Resource Allocation of not just Simple-V but the 80-100 Scalar instructions all at the same time*. -# Resources +It is also critical to note that Simple-V **does not modify the Scalar Power ISA +in any way**. There is one sole semi-exception to that (Vectorised Branch Conditional) +in order to provide the usual capability present in every Commercial 3D GPU ISA. +# Compliancy Levels + +Simple-V has been subdivided into levels akin to the Power ISA Compliancy Levels. +For now Let us call them "SV Compliancy Levels" to distinguish the two. The reason for +the SV Compliancy Levels is the same as for the Power ISA Compliancy Levels (SFFS, SFS): +to not overburden implementors with features that they do not need. +*There is no dependence between the two types of Compliancy Levels* + +The resources below therefore are not all required for all SV Compliancy Levels but +they are all required + +# Simple-V Resources + +* No new Interrupt types are required. +* Register numbers are extended to 128 (including CR Fields). + A future version may extend to 256 or beyond [^extend] + + +[^extend]: Prefix opcode space **must** be reserved in advance to to so, in order to avoid the catastrophic mistake made by RISC-V RVV and ARM SVE/2 -- 2.30.2