From b81f1ee3b33dd046db7f508ebf0e29d0e12c406d Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Mon, 28 Sep 2015 09:35:46 +0000 Subject: [PATCH] [Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attribute gcc/ * config/arm/types.md (type): Add rotate_imm. * config/aarch64/aarch64.md (*ror3_insn): Split out the ROR immediate case. (*rorsi3_insn_uxtw): Likewise. * config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm. * config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm. * config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm. From-SVN: r228197 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/aarch64/aarch64.md | 14 +++++++------- gcc/config/aarch64/thunderx.md | 2 +- gcc/config/arm/cortex-a53.md | 2 +- gcc/config/arm/cortex-a57.md | 2 +- gcc/config/arm/types.md | 2 ++ 6 files changed, 22 insertions(+), 10 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 32875dfca72..e066bd76b82 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2015-09-28 James Greenhalgh + + * config/arm/types.md (type): Add rotate_imm. + * config/aarch64/aarch64.md (*ror3_insn): Split out the + ROR immediate case. + (*rorsi3_insn_uxtw): Likewise. + * config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm. + * config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm. + * config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm. + 2015-09-28 Kyrylo Tkachov PR rtl-optimization/67481 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3e8520905b7..e5179dd2bbb 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3807,13 +3807,13 @@ ;; Rotate right (define_insn "*ror3_insn" - [(set (match_operand:GPI 0 "register_operand" "=r") - (rotatert:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r") + (rotatert:GPI + (match_operand:GPI 1 "register_operand" "r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "r,Us")))] "" "ror\\t%0, %1, %2" - [(set_attr "type" "shift_reg")] + [(set_attr "type" "shift_reg, rotate_imm")] ) ;; zero_extend version of above @@ -3902,7 +3902,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "ror\\t%0, %1, %3"; } - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) ;; zero_extend version of the above @@ -3916,7 +3916,7 @@ operands[3] = GEN_INT (32 - UINTVAL (operands[2])); return "ror\\t%w0, %w1, %3"; } - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) (define_insn "*_ashl" diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index cf9636862f2..3dae963fc91 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -39,7 +39,7 @@ (define_insn_reservation "thunderx_shift" 1 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "bfm,extend,shift_imm,shift_reg,rbit,rev")) + (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev")) "thunderx_pipe0 | thunderx_pipe1") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index db572f68052..3fa0625c130 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -76,7 +76,7 @@ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,csel,clz,rbit,rev,alu_dsp_reg,\ - shift_imm,shift_reg,\ + rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mrs,multiple,no_insn")) "cortex_a53_slot_any") diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index a32c848756b..d6ce4402125 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -296,7 +296,7 @@ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\ - shift_imm,shift_reg,\ + rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ mrs,multiple,no_insn")) diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index ec609aeaed1..534be74fe46 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -120,6 +120,7 @@ ; final output, thus having no impact on scheduling. ; rbit reverse bits. ; rev reverse bytes. +; rotate_imm rotate by immediate. ; sdiv signed division. ; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an ; immediate. @@ -627,6 +628,7 @@ nop,\ rbit,\ rev,\ + rotate_imm,\ sdiv,\ shift_imm,\ shift_reg,\ -- 2.30.2