From b860e0ba3769202d31d9b55c3ee36d8e47446c06 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 5 Feb 2015 11:46:02 +0100 Subject: [PATCH] mac/core: fix condition of insertion for last_be/converter --- liteeth/mac/core/__init__.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py index 7a420de1..98828ad8 100644 --- a/liteeth/mac/core/__init__.py +++ b/liteeth/mac/core/__init__.py @@ -27,13 +27,17 @@ class LiteEthMACCore(Module, AutoCSR): tx_pipeline += [preamble_inserter, crc32_inserter] rx_pipeline += [preamble_checker, crc32_checker] - if dw != phy.dw: + if dw != 8: # Delimiters tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw) rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw) self.submodules += RenameClockDomains(tx_last_be, "eth_tx") self.submodules += RenameClockDomains(rx_last_be, "eth_rx") + tx_pipeline += [tx_last_be] + rx_pipeline += [rx_last_be] + + if dw != phy.dw: # Converters reverse = endianness == "be" tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse) @@ -41,8 +45,8 @@ class LiteEthMACCore(Module, AutoCSR): self.submodules += RenameClockDomains(tx_converter, "eth_tx") self.submodules += RenameClockDomains(rx_converter, "eth_rx") - tx_pipeline += [tx_last_be, tx_converter] - rx_pipeline += [rx_last_be, rx_converter] + tx_pipeline += [tx_converter] + rx_pipeline += [rx_converter] # Cross Domain Crossing tx_cdc = AsyncFIFO(eth_phy_description(dw), 4) -- 2.30.2